LPC Interface Bridge Registers (D31:F0)
13.8.3.6
LV2 — Level 2 Register
I/O Address:
PMBASE + 14h
(ACPI P_BLK+4)
Attribute:
Size:
Usage:
RO
Default Value:
Lockable:
Power Well:
00h
No
Core
8-bit
ACPI or Legacy
Bit
Description
Reads to this register return all 0s, writes to this register have no effect. Reads to this
register generate a “enter a level 2 power state” (C2) to the clock control logic. This will
cause the STPCLK# signal to go active, and stay active until a break event occurs.
Throttling (due either to THTL_EN or FORCE_THTL) will be ignored.
7:0
NOTE: This register should not be used by IA-64 processors or systems with more than 1 logical
processor, unless appropriate semaphoring software has been put in place to ensure that
all threads/processors are ready for the C2 state when the read to this register occurs
13.8.3.7
LV3—Level 3 Register
I/O Address:
PMBASE + 15h (ACPI P_BLK + 5)
Attribute:
RO
Default Value:
Lockable:
00h
No
Size:
8-bit
Usage:
Power Well:
ACPI or Legacy
Core
Bit
Description
Reads to this register return all 0s, writes to this register have no effect. Reads to this
register generate a “enter a C3 power state” to the clock control logic. The C3 state
persists until a break event occurs.
7:0
NOTE: If the C4onC3_EN bit is set, reads this register will initiate a LVL4 transition rather than a
LVL3 transition. In the event that software attempts to simultaneously read the LVL2 and
LVL3 registers (which is invalid), the ICH10 will ignore the LVL3 read, and only perform a
C2 transition.
NOTE: This register should not be used by IA-64 processors or systems with more than 1 logical
processor, unless appropriate semaphoring software has been put in place to ensure that
all threads/processors are ready for the C3 state when the read to this register occurs.
13.8.3.8
LV4—Level 4 Register
I/O Address:
PMBASE + 16h (ACPI P_BLK + 6)
Attribute:
RO
Default Value:
Lockable:
00h
No
Size:
8-bit
Usage:
Power Well:
ACPI or Legacy
Core
Bit
Description
Reads to this register return all 0s, writes to this register have no effect. Reads to this
register generate a “enter a C4 power state” to the clock control logic. The C4 state
persists until a break event occurs.
7:0
NOTE: This register should not be used by IA-64 processors or systems with more than 1 logical
processor, unless appropriate semaphoring software has been put in place to ensure that
all threads/processors are ready for the C4 state when the read to this register occurs.
Datasheet
469
INTEL [ INTEL ]
