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319973-003 参数 Datasheet PDF下载

319973-003图片预览
型号: 319973-003
PDF下载: 下载PDF文件 查看货源
内容描述: 英特尔I / O控制器中枢10 [Intel I/O Controller Hub 10]
分类和应用: 控制器
文件页数/大小: 840 页 / 5889 K
品牌: INTEL [ INTEL ]
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LPC Interface Bridge Registers (D31:F0)  
13.8.3.3  
PM1_CNT—Power Management 1 Control  
I/O Address:  
PMBASE + 04h  
(ACPI PM1a_CNT_BLK)  
00000000h  
Attribute:  
R/W, WO  
Default Value:  
Lockable:  
Power Well:  
Size:  
32-bit  
No  
Usage:  
ACPI or Legacy  
Bits 07: Core,  
Bits 812: RTC,  
Bits 1315: Resume  
Bit  
Description  
31:14  
13  
Reserved.  
Sleep Enable (SLP_EN) — WO. Setting this bit causes the system to sequence into  
the Sleep state defined by the SLP_TYP field.  
Sleep Type (SLP_TYP) — R/W. This 3-bit field defines the type of Sleep the  
system should enter when the SLP_EN bit is set to 1. These bits are only reset by  
RTCRST#.  
Code  
Master Interrupt  
000b  
ON: Typically maps to S0 state.  
Asserts STPCLK#. Puts processor in Stop-Grant state. Optional to  
assert CPUSLP# to put processor in sleep state: Typically maps to S1  
state.  
001b  
12:10  
010b  
011b  
100b  
101b  
Reserved  
Reserved  
Reserved  
Suspend-To-RAM. Assert SLP_S3#: Typically maps to S3 state.  
Suspend-To-Disk. Assert SLP_S3#, and SLP_S4#: Typically maps to  
S4 state.  
110b  
111b  
Soft Off. Assert SLP_S3#, SLP_S4#, and SLP_S5#: Typically maps to  
S5 state.  
9:3  
2
Reserved.  
Global Release (GBL_RLS) — WO.  
0 = This bit always reads as 0.  
1 = ACPI software writes a 1 to this bit to raise an event to the BIOS. BIOS software  
has a corresponding enable and status bits to control its ability to receive ACPI  
events.  
Bus Master Reload (BM_RLD) — R/W. This bit is treated as a scratchpad bit. This  
bit is reset to 0 by PLTRST#  
0 = Bus master requests will not cause a break from the C3 state.  
1 = Enables Bus Master requests (internal or external) to cause a break from the C3  
state.  
1
0
If software fails to set this bit before going to C3 state, ICH10 will still return to a  
snoopable state from C3 or C4 states due to bus master activity.  
SCI Enable (SCI_EN) — R/W. Selects the SCI interrupt or the SMI# interrupt for  
various events including the bits in the PM1_STS register (bit 10, 8, 0), and bits in  
GPE0_STS.  
0 = These events will generate an SMI#.  
1 = These events will generate an SCI.  
466  
Datasheet  
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