LPC Interface Bridge Registers (D31:F0)
13.8.3.4
PM1_TMR—Power Management 1 Timer Register
I/O Address:
PMBASE + 08h
(ACPI PMTMR_BLK)
Attribute:
Size:
Usage:
RO
32-bit
ACPI
Default Value:
Lockable:
Power Well:
xx000000h
No
Core
Bit
Description
31:24 Reserved
Timer Value (TMR_VAL) — RO. Returns the running count of the PM timer. This
counter runs off a 3.579545 MHz clock (14.31818 MHz divided by 4). It is reset to 0
during a PCI reset, and then continues counting as long as the system is in the S0
state. After an S1 state, the counter will not be reset (it will continue counting from the
last value in S0 state.
23:0
Anytime bit 22 of the timer goes HIGH to LOW (bits referenced from 0 to 23), the
TMROF_STS bit (PMBASE + 00h, bit 0) is set. The High-to-Low transition will occur
every 2.3435 seconds. If the TMROF_EN bit (PMBASE + 02h, bit 0) is set, an SCI
interrupt is also generated.
13.8.3.5
PROC_CNT—Processor Control Register
I/O Address:
PMBASE + 10h
(ACPI P_BLK)
00000000h
No (bits 7:5 are write once)Usage:
Core
Attribute:
Size:
R/W, RO, WO
32-bit
ACPI or Legacy
Default Value:
Lockable:
Power Well:
Bit
Description
31:18 Reserved
Throttle Status (THTL_STS) — RO.
0 = No clock throttling is occurring (maximum processor performance).
1 = Indicates that the clock state machine is throttling the processor performance. This
could be due to the THT_EN bit or the FORCE_THTL bit being set.
17
16:9
Reserved
Force Thermal Throttling (FORCE_THTL) — R/W. Software can set this bit to force
the thermal throttling function.
8
0 = No forced throttling.
1 = Throttling at the duty cycle specified in THRM_DTY starts immediately, and no
SMI# is generated.
Datasheet
467
INTEL [ INTEL ]
