LPC Interface Bridge Registers (D31:F0)
13.5.5
ID—Identification Register (LPC I/F—D31:F0)
Index Offset:
Default Value:
00h
00000000h
Attribute:
Size:
R/W
32 bits
The APIC ID serves as a physical name of the APIC. The APIC bus arbitration ID for the
APIC is derived from its I/O APIC ID. This register is reset to 0 on power-up reset.
Bit
Description
31:28 Reserved
27:24 APIC ID — R/W. Software must program this value before using the APIC.
23:16 Reserved
15
Scratchpad Bit.
14:0 Reserved
13.5.6
VER—Version Register (LPC I/F—D31:F0)
Index Offset:
Default Value:
01h
00170020h
Attribute:
Size:
RO, RWO
32 bits
Each I/O APIC contains a hardwired Version Register that identifies different
implementation of APIC and their versions. The maximum redirection entry information
also is in this register, to let software know how many interrupt are supported by this
APIC.
Bit
Description
31:24 Reserved
Maximum Redirection Entries (MRE) — RWO. This is the entry number (0 being the
lowest entry) of the highest entry in the redirection table. It is equal to the number of
interrupt input pins minus one and is in the range 0 through 239. In the ICH10 this field
is hardwired to 17h to indicate 24 interrupts.
23:16
BIOS must write to this field after PLTRST# to lockdown the value. this allows BIOS to
utilize some of the entries for its own purpose and thus advertising fewer IOxAPIC
Redirection Entries to the OS.
Pin Assertion Register Supported (PRQ) — RO. Indicate that the IOxAPIC does not
implement the Pin Assertion Register.
15
14:8 Reserved
Version (VS) — RO. This is a version number that identifies the implementation
version.
7:0
436
Datasheet
INTEL [ INTEL ]
