LPC Interface Bridge Registers (D31:F0)
13.4.11 ELCR2—Slave Controller Edge/Level Triggered Register
(LPC I/F—D31:F0)
Offset Address: 4D1h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In
level mode (bit[x] = 1), the interrupt is recognized by a high level. The real time clock,
IRQ8#, and the floating point error interrupt, IRQ13, cannot be programmed for level
mode.
Bit
Description
IRQ15 ECL — R/W.
7
0 = Edge
1 = Level
IRQ14 ECL — R/W.
6
5
4
0 = Edge
1 = Level
Reserved. Must be 0.
IRQ12 ECL — R/W.
0 = Edge
1 = Level
IRQ11 ECL — R/W.
3
2
0 = Edge
1 = Level
IRQ10 ECL — R/W.
0 = Edge
1 = Level
IRQ9 ECL — R/W.
1
0
0 = Edge
1 = Level
Reserved. Must be 0.
432
Datasheet
INTEL [ INTEL ]
