LPC Interface Bridge Registers (D31:F0)
13.5.4
EOIR—EOI Register (LPC I/F—D31:F0)
Memory Address FEC0_0000h (Consumer Only) Attribute:
FEC_ _0000h (Corporate Only)
R/W
Default Value:
N/A
Size:
32 bits
The EOI register is present to provide a mechanism to maintain the level triggered
semantics for level-triggered interrupts issued on the parallel bus.
When a write is issued to this register, the I/O APIC will check the lower 8 bits written
to this register, and compare it with the vector field for each entry in the I/O
Redirection Table. When a match is found, the Remote_IRR bit (Index Offset 10h, bit
14) for that I/O Redirection Entry will be cleared.
Note:
Note:
If multiple I/O Redirection entries, for any reason, assign the same vector for more
than one interrupt input, each of those entries will have the Remote_IRR bit reset to 0.
The interrupt which was prematurely reset will not be lost because if its input remained
active when the Remote_IRR bit is cleared, the interrupt will be reissued and serviced
at a later time. Note: Only bits 7:0 are actually used. Bits 31:8 are ignored by the
ICH10.
To provide for future expansion, the processor should always write a value of 0 to Bits
31:8.
Bit
Description
Reserved. To provide for future expansion, the processor should always write a value of
0 to Bits 31:8.
31:8
Redirection Entry Clear — WO. When a write is issued to this register, the I/O APIC
will check this field, and compare it with the vector field for each entry in the I/O
Redirection Table. When a match is found, the Remote_IRR bit for that I/O Redirection
Entry will be cleared.
7:0
Datasheet
435
INTEL [ INTEL ]
