LPC Interface Bridge Registers (D31:F0)
Bit
Description
Destination Mode — R/W. This field determines the interpretation of the Destination
field.
0 = Physical. Destination APIC ID is identified by bits 59:56.
1 = Logical. Destinations are identified by matching bit 63:56 with the Logical
Destination in the Destination Format Register and Logical Destination Register in
each Local APIC.
11
Delivery Mode — R/W. This field specifies how the APICs listed in the destination field
should act upon reception of this signal. Certain Delivery Modes will only operate as
intended when used in conjunction with a specific trigger mode. These encodings are
listed in the note below:
10:8
7:0
Vector — R/W. This field contains the interrupt vector for this interrupt. Values range
between 10h and FEh.
NOTE: Delivery Mode encoding:
000 = Fixed. Deliver the signal on the INTR signal of all processor cores listed in the destination.
Trigger Mode can be edge or level.
001 = Lowest Priority. Deliver the signal on the INTR signal of the processor core that is
executing at the lowest priority among all the processors listed in the specified destination.
Trigger Mode can be edge or level.
010 = SMI (System Management Interrupt). Requires the interrupt to be programmed as edge
triggered. The vector information is ignored but must be programmed to all 0s for future
compatibility: not supported
011 = Reserved
100 = NMI. Deliver the signal on the NMI signal of all processor cores listed in the destination.
Vector information is ignored. NMI is treated as an edge triggered interrupt even if it is
programmed as level triggered. For proper operation this redirection table entry must be
programmed to edge triggered. The NMI delivery mode does not set the RIRR bit. If the
redirection table is incorrectly set to level, the loop count will continue counting through
the redirection table addresses. Once the count for the NMI pin is reached again, the
interrupt will be sent again: not supported
101 = INIT. Deliver the signal to all processor cores listed in the destination by asserting the INIT
signal. All addressed local APICs will assume their INIT state. INIT is always treated as an
edge triggered interrupt even if programmed as level triggered. For proper operation this
redirection table entry must be programmed to edge triggered. The INIT delivery mode
does not set the RIRR bit. If the redirection table is incorrectly set to level, the loop count
will continue counting through the redirection table addresses. Once the count for the INIT
pin is reached again, the interrupt will be sent again: not supported
110 = Reserved
111 = ExtINT. Deliver the signal to the INTR signal of all processor cores listed in the destination
as an interrupt that originated in an externally connected 8259A compatible interrupt
controller. The INTA cycle that corresponds to this ExtINT delivery will be routed to the
external controller that is expected to supply the vector. Requires the interrupt to be
programmed as edge triggered.
438
Datasheet
INTEL [ INTEL ]
