LPC Interface Bridge Registers (D31:F0)
13.4
8259 Interrupt Controller (PIC) Registers
(LPC I/F—D31:F0)
13.4.1
Interrupt Controller I/O MAP (LPC I/F—D31:F0)
The interrupt controller registers are located at 20h and 21h for the master controller
(IRQ 0–7), and at A0h and A1h for the slave controller (IRQ 8–13). These registers
have multiple functions, depending upon the data written to them. Table 13-3 shows
the different register possibilities for each address.
Table 13-3. PIC Registers (LPC I/F—D31:F0)
Default
Value
Port
Aliases
Register Name
Type
Master PIC ICW1 Init. Cmd Word 1
Master PIC OCW2 Op Ctrl Word 2
Master PIC OCW3 Op Ctrl Word 3
Master PIC ICW2 Init. Cmd Word 2
Master PIC ICW3 Init. Cmd Word 3
Master PIC ICW4 Init. Cmd Word 4
Master PIC OCW1 Op Ctrl Word 1
Slave PIC ICW1 Init. Cmd Word 1
Slave PIC OCW2 Op Ctrl Word 2
Undefined
001XXXXXb
X01XXX10b
Undefined
Undefined
01h
WO
WO
WO
WO
WO
WO
R/W
WO
WO
24h, 28h,
2Ch, 30h,
20h
34h, 38h, 3Ch
25h, 29h,
2Dh, 31h,
21h
A0h
A1h
35h, 39h,
3Dh
00h
A4h, A8h,
ACh, B0h,
Undefined
001XXXXXb
B4h, B8h,
BCh
Slave PIC OCW3 Op Ctrl Word 3
X01XXX10b
WO
Slave PIC ICW2 Init. Cmd Word 2
Slave PIC ICW3 Init. Cmd Word 3
Slave PIC ICW4 Init. Cmd Word 4
Slave PIC OCW1 Op Ctrl Word 1
Master PIC Edge/Level Triggered
Slave PIC Edge/Level Triggered
Undefined
Undefined
01h
WO
WO
A5h, A9h,
ADh, B1h,
B5h, B9h,
BDh
WO
00h
R/W
R/W
R/W
4D0h
4D1h
–
–
00h
00h
Note:
Refer to note addressing active-low interrupt sources in 8259 Interrupt Controllers
section (Section 5.8).
424
Datasheet
INTEL [ INTEL ]
