LPC Interface Bridge Registers (D31:F0)
13.2
DMA I/O Registers (LPC I/F—D31:F0)
Table 13-2. DMA Registers (Sheet 1 of 2)
Port
Alias
Register Name
Default
Type
Channel 0 DMA Base & Current Address
Channel 0 DMA Base & Current Count
Channel 1 DMA Base & Current Address
Channel 1 DMA Base & Current Count
Channel 2 DMA Base & Current Address
Channel 2 DMA Base & Current Count
Channel 3 DMA Base & Current Address
Channel 3 DMA Base & Current Count
Channel 0–3 DMA Command
00h
01h
02h
03h
04h
05h
06h
07h
10h
11h
12h
13h
14h
15h
16h
17h
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
000001XXb
000000XXb
Undefined
Undefined
Undefined
0Fh
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WO
08h
18h
Channel 0–3 DMA Status
RO
Channel 0–3 DMA Write Single Mask
Channel 0–3 DMA Channel Mode
Channel 0–3 DMA Clear Byte Pointer
Channel 0–3 DMA Master Clear
Channel 0–3 DMA Clear Mask
0Ah
0Bh
1Ah
1Bh
WO
WO
0Ch
1Ch
1Dh
1Eh
WO
0Dh
0Eh
WO
WO
Channel 0–3 DMA Write All Mask
Reserved Page
0Fh
1Fh
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
80h
90h
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Channel 2 DMA Memory Low Page
Channel 3 DMA Memory Low Page
Channel 1 DMA Memory Low Page
Reserved Pages
81h
91h
82h
—
83h
93h
84h–86h
87h
94h–96h
97h
Channel 0 DMA Memory Low Page
Reserved Page
88h
98h
Channel 6 DMA Memory Low Page
Channel 7 DMA Memory Low Page
Channel 5 DMA Memory Low Page
Reserved Page
89h
99h
8Ah
9Ah
8Bh
9Bh
8Ch–8Eh
8Fh
9Ch–9Eh
9Fh
Refresh Low Page
Channel 4 DMA Base & Current Address
Channel 4 DMA Base & Current Count
Channel 5 DMA Base & Current Address
Channel 5 DMA Base & Current Count
Channel 6 DMA Base & Current Address
Channel 6 DMA Base & Current Count
Channel 7 DMA Base & Current Address
C0h
C1h
C3h
C5h
C7h
C9h
CBh
CDh
C2h
C4h
C6h
C8h
CAh
CCh
Datasheet
411
INTEL [ INTEL ]
