LPC Interface Bridge Registers (D31:F0)
13.1.35 FDVCT—Feature Vector
(LPC I/F—D31:F0)
Offset Address: E4h-EBh
Attribute:
RO
64 bit
Core
Default Value:
See Description
Size:
Power Well:
Bit
Description
63:42 Reserved
Intel® Active Management Technology Release 5.0 Support Capability — RO.
41
0 = Professional
1 = Basic
40:38 Reserved
Intel Active Management Technology Capability — RO.
37
36:6
5
0 = Capable
1 = Disabled
Reserved
SATA RAID 0/1/5/10 Capability— RO.
0 = Capable
1 = Disabled
4:0
Reserved
13.1.36 RCBA—Root Complex Base Address Register
(LPC I/F—D31:F0)
Offset Address: F0-F3h
Attribute:
Size:
R/W
32 bit
Default Value:
00000000h
Bit
Description
Base Address (BA) — R/W. Base Address for the root complex register block decode
range. This address is aligned on a 16-KB boundary.
31:14
13:1
0
Reserved
Enable (EN) — R/W. When set, enables the range specified in BA to be claimed as the
Root Complex Register Block.
410
Datasheet
INTEL [ INTEL ]
