LPC Interface Bridge Registers (D31:F0)
13.2.6
DMA_WRSMSK—DMA Write Single Mask Register
(LPC I/F—D31:F0)
I/O Address:
Ch. #0–3 = 0Ah;
Ch. #4–7 = D4h
0000 01xx
No
Attribute:WO
Size: 8-bit
Power Well:Core
Default Value:
Lockable:
Bit
Description
7:3
Reserved. Must be 0.
Channel Mask Select — WO.
0 = Enable DREQ for the selected channel. The channel is selected through bits [1:0].
Therefore, only one channel can be masked / unmasked at a time.
1 = Disable DREQ for the selected channel.
2
DMA Channel Select — WO. These bits select the DMA Channel Mode Register to
program.
00 = Channel 0 (4)
01 = Channel 1 (5)
10 = Channel 2 (6)
11 = Channel 3 (7)
1:0
Datasheet
415
INTEL [ INTEL ]
