LPC Interface Bridge Registers (D31:F0)
13.1.30 FWH_DEC_EN1—Firmware Hub Decode Enable Register
(LPC I/F—D31:F0)
Offset Address: D8h–D9h
Attribute:
Size:
R/W, RO
16 bits
Default Value:
FFCFh
Bit
Description
FWH_F8_EN — RO. This bit enables decoding two 512-KB Firmware Hub memory
ranges, and one 128-KB memory range.
0 = Disable
15
14
13
12
11
10
9
1 = Enable the following ranges for the Firmware Hub
FFF80000h – FFFFFFFFh
FFB80000h – FFBFFFFFh
FWH_F0_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory
ranges.
0 = Disable.
1 = Enable the following ranges for the Firmware Hub:
FFF00000h – FFF7FFFFh
FFB00000h – FFB7FFFFh
FWH_E8_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory
ranges.
0 = Disable.
1 = Enable the following ranges for the Firmware Hub:
FFE80000h – FFEFFFFh
FFA80000h – FFAFFFFFh
FWH_E0_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory
ranges.
0 = Disable.
1 = Enable the following ranges for the Firmware Hub:
FFE00000h – FFE7FFFFh
FFA00000h – FFA7FFFFh
FWH_D8_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory
ranges.
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
FFD80000h – FFDFFFFFh
FF980000h – FF9FFFFFh
FWH_D0_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory
ranges.
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
FFD00000h – FFD7FFFFh
FF900000h – FF97FFFFh
FWH_C8_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory
ranges.
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
FFC80000h – FFCFFFFFh
FF880000h – FF8FFFFFh
406
Datasheet
INTEL [ INTEL ]
