Gigabit LAN Configuration Registers
12.1.22 DR—Data Register
(Gigabit LAN—D25:F0)
Address Offset: CFh
Attribute:
Size:
RO
8 bits
Default Value:
See bit description
Bit
Description
Reported Data (RD) — RO. This register is used to report power consumption and
heat dissipation. This register is controlled by the Data_Select field in the PMCS (Offset
CCh, bits 12:9), and the power scale is reported in the Data_Scale field in the PMCS
(Offset CCh, bits 14:13). The data of this field is loaded from the NVM if PM is enabled
in the NVM or with a default value of 00h otherwise.
7:0
12.1.23 CLIST 2—Capabilities List Register 2
(Gigabit LAN—D25:F0)
Address Offset:
Default Value:
D0h–D1h
E005h
Attribute:
Size:
R/WO, RO
16 bits
Function Level Reset: No (Bits 15:8 only)
Bit
Description
Next Capability (NEXT) — R/WO. Value of E0h points to the Function Level Reset
capability structure.
15:8
These bits are not reset by Function Level Reset.
Capability ID (CID) — RO. Indicates the linked list item is a Message Signaled
Interrupt Register.
7:0
12.1.24 MCTL—Message Control Register
(Gigabit LAN—D25:F0)
Address Offset: D2h–D3h
Attribute:
Size:
R/W, RO
16 bits
Default Value:
0080h
Bit
Description
15:8
7
Reserved
64-bit Capable (CID) — RO. Set to ‘1’ to indicate that the GbE LAN Controller is
capable of generating 64-bit message addresses.
Multiple Message Enable (MME) — RO. Returns 000b to indicate that the GbE LAN
controller only supports a single message.
6:4
3:1
Multiple Message Capable (MMC) — RO. The GbE LAN controller does not support
multiple messages.
MSI Enable (MSIE) — R/W.
0 = MSI generation is disabled.
1 = The Gb LAN controller will generate MSI for interrupt assertion instead of INTx
signaling.
0
Datasheet
381
INTEL [ INTEL ]
