PCI-to-PCI Bridge Registers (D30:F0)
Bit
Description
VGA Enable (VGAE) — R/W. When set to a 1, the ICH10 PCI bridge forwards the
following transactions to PCI regardless of the value of the I/O base and limit registers.
The transactions are qualified by CMD.MSE (D30:F0:04 bit 1) and CMD.IOSE
(D30:F0:04 bit 0) being set.
•
•
Memory addresses: 000A0000h-000BFFFFh
I/O addresses: 3B0h-3BBh and 3C0h-3DFh. For the I/O addresses, bits [63:16] of the address
must be 0, and bits [15:10] of the address are ignored (i.e., aliased).
3
The same holds true from secondary accesses to the primary interface in reverse. That
is, when the bit is 0, memory and I/O addresses on the secondary interface between
the above ranges will be claimed.
ISA Enable (IE) — R/W. This bit only applies to I/O addresses that are enabled by the
I/O Base and I/O Limit registers and are in the first 64 KB of PCI I/O space. If this bit is
set, the ICH10 PCI bridge will block any forwarding from primary to secondary of I/O
transactions addressing the last 768 bytes in each 1-KB block (offsets 100h to 3FFh).
2
1
0
SERR# Enable (SEE) — R/W. This bit controls the forwarding of secondary interface
SERR# assertions on the primary interface. When set, the PCI bridge will forward
SERR# pin.
•
•
•
SERR# is asserted on the secondary interface.
This bit is set.
CMD.SEE (D30:F0:04 bit 8) is set.
Parity Error Response Enable (PERE) — R/W.
0 = Disable
1 = The ICH10 PCI bridge is enabled for parity error reporting based on parity errors on
the PCI bus.
11.1.20 SPDH—Secondary PCI Device Hiding Register
(PCI-PCI—D30:F0)
Offset Address: 40h–41h
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
This register allows software to hide the PCI devices, either plugged into slots or on the
motherboard.
Bit
Description
15:4
Reserved
Hide Device 3 (HD3) — R/W, RO. Same as bit 0 of this register, except for device 3
(AD[19])
3
2
1
Hide Device 2 (HD2) — R/W, RO. Same as bit 0 of this register, except for device 2
(AD[18])
Hide Device 1 (HD1) — R/W, RO. Same as bit 0 of this register, except for device 1
(AD[17])
Hide Device 0 (HD0) — R/W, RO.
0 = The PCI configuration cycles for this slot are not affected.
1 = Intel® ICH10 hides device 0 on the PCI bus. This is done by masking the IDSEL
(keeping it low) for configuration cycles to that device. Since the device will not see
its IDSEL go active, it will not respond to PCI configuration cycles and the
processor will think the device is not present. AD[16] is used as IDSEL for device 0.
0
366
Datasheet
INTEL [ INTEL ]
