Functional Description
Table 5-45. USB Legacy Keyboard State Transitions (Sheet 2 of 2)
Current
State
Data
Value
Next
State
Action
Comment
Cycle passed through to 8042, even if trap
enabled via Bit 3 in Config Register. No
GateState1 SMI# generated. PSTATE remains 1. Stay in
GateState1 because this is part of the
double-trigger sequence.
64h /
Write
GateState1
GateState1
D1h
Not D1h
N/A
Bit 3 in Config space determines if cycle
passed through to 8042 and if SMI#
generated. PSTATE goes to 0. If Bit 7 in
Config Register is set, then SMI# should be
generated.
64h /
Write
ILDE
IDLE
This is an invalid sequence. Bit 0 in Config
Register determines if cycle passed through
to 8042 and if SMI# generated. PSTATE
goes to 0. If Bit 7 in Config Register is set,
then SMI# should be generated.
GateState1 60h / Read
Just stay in same state. Generate an SMI#
GateState1 64h / Read
GateState2 64 / Write
N/A
FFh
GateState1 if enabled in Bit 2 of Config Register. PSTATE
remains 1.
Standard end of sequence. Cycle passed
through to 8042. PSTATE goes to 0. Bit 7 in
Config Space determines if SMI# should be
IDLE
generated.
Improper end of sequence. Bit 3 in Config
Register determines if cycle passed through
to 8042 and if SMI# generated. PSTATE
goes to 0. If Bit 7 in Config Register is set,
then SMI# should be generated.
64h /
GateState2
Not FFh
N/A
IDLE
Write
Just stay in same state. Generate an SMI#
GateState2 if enabled in Bit 2 of Config Register. PSTATE
remains 1.
GateState2 64h / Read
Improper end of sequence. Bit 1 in Config
Register determines if cycle passed through
to 8042 and if SMI# generated. PSTATE
goes to 0. If Bit 7 in Config Register is set,
then SMI# should be generated.
60h /
GateState2
XXh
IDLE
IDLE
Write
Improper end of sequence. Bit 0 in Config
Register determines if cycle passed through
to 8042 and if SMI# generated. PSTATE
goes to 0. If Bit 7 in Config Register is set,
then SMI# should be generated.
GateState2 60h / Read
N/A
Datasheet
199
INTEL [ INTEL ]
