Functional Description
5.19.1.3
EHC Resets
In addition to the standard ICH10 hardware resets, portions of the EHC are reset by the
HCRESET bit and the transition from the D3HOT device power management state to the
D0 state. The effects of each of these resets are:
Reset
Does Reset
Does not Reset
Comments
Memory space
registers except
Structural
Parameters (which is
written by BIOS).
The HCRESET must only affect
registers that the EHCI driver
controls. PCI Configuration
space and BIOS-programmed
parameters can not be reset.
Configuration
registers.
HCRESET bit set.
The D3-to-D0 transition must
not cause wake information
(suspend well) to be lost. It also
must not clear BIOS-
Software writes
the Device Power
State from D3HOT
(11b) to D0
Core well registers
(except BIOS-
programmed
registers).
Suspend well
registers; BIOS-
programmed core programmed registers because
well registers.
BIOS may not be invoked
following the D3-to-D0
transition.
(00b).
If the detailed register descriptions give exceptions to these rules, those exceptions
override these rules. This summary is provided to help explain the reasons for the reset
policies.
5.19.2
5.19.3
Data Structures in Main Memory
See Section 3 and Appendix B of the Enhanced Host Controller Interface Specification
for Universal Serial Bus, Revision 1.0 for details.
USB 2.0 Enhanced Host Controller DMA
The ICH10 USB 2.0 EHC implements three sources of USB packets. They are, in order
of priority on USB during each microframe:
1. The USB 2.0 Debug Port (see Section USB 2.0 Based Debug Port),
2. The Periodic DMA engine, and
3. The Asynchronous DMA engine.
The ICH10 always performs any currently-pending debug port transaction at the
beginning of a microframe, followed by any pending periodic traffic for the current
microframe. If there is time left in the microframe, then the EHC performs any pending
asynchronous traffic until the end of the microframe (EOF1). Note that the debug port
traffic is only presented on one port (Port #0), while the other ports are idle during this
time.
5.19.4
Data Encoding and Bit Stuffing
See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0.
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Datasheet
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