Functional Description
5.18.7
USB Power Management
The Host controller can be put into a suspended state and its power can be removed.
This requires that certain bits of information are retained in the suspend power plane of
the ICH10 so that a device on a port may wake the system. Such a device may be a
fax-modem, which will wake up the machine to receive a fax or take a voice message.
The settings of the following bits in I/O space will be maintained when the ICH10 enters
the S3, S4, or S5 states.
Table 5-44. Bits Maintained in Low Power States
Register
Offset
Bit
Description
Command
Status
00h
02h
3
2
Enter Global Suspend Mode (EGSM)
Resume Detect
2
Port Enabled/Disabled
Resume Detect
6
Port Status and
Control
10h & 12h
8
Low-speed Device Attached
Suspend
12
When the ICH10 detects a resume event on any of its ports, it sets the corresponding
USB_STS bit in ACPI space. If USB is enabled as a wake/break event, the system
wakes up and an SCI generated.
5.18.8
USB Legacy Keyboard Operation
When a USB keyboard is plugged into the system, and a standard keyboard is not, the
system may not boot, and MS-DOS legacy software will not run, because the keyboard
will not be identified. The ICH10 implements a series of trapping operations which will
snoop accesses that go to the keyboard controller, and put the expected data from the
USB keyboard into the keyboard controller.
Note:
The scheme described below assumes that the keyboard controller (8042 or
equivalent) is on the LPC bus.
This legacy operation is performed through SMM space. Figure 5-13 shows the Enable
and Status path. The latched SMI source (60R, 60W, 64R, 64W) is available in the
Status Register. Because the enable is after the latch, it is possible to check for other
events that didn't necessarily cause an SMI. It is the software's responsibility to
logically AND the value with the appropriate enable bits.
Note also that the SMI is generated before the PCI cycle completes (e.g., before TRDY#
goes active) to ensure that the processor doesn't complete the cycle before the SMI is
observed.
The logic also needs to block the accesses to the 8042. If there is an external 8042,
then this is simply accomplished by not activating the 8042 CS. This is done by logically
ANDing the four enables (60R, 60W, 64R, 64W) with the 4 types of accesses to
determine if 8042CS should go active. An additional term is required for the “pass-
through” case.
The state table for Figure 5-13 is shown in Table 5-45.
Datasheet
197
INTEL [ INTEL ]
