Functional Description
Figure 5-13. USB Legacy Keyboard Flow Diagram
To Individual
"Caused By"
"Bits"
60 READ
KBC Accesses
S
R
D
Clear SMI_60_R
AND
PCI Config
Comb.
Decoder
EN_SMI_ON_60R
Read, Write
SMI
OR
Same for 60W, 64R, 64W
EN_PIRQD#
AND
To PIRQD#
To "Caused By" Bit
USB_IRQ
Clear USB_IRQ
S
R
D
AND
EN_SMI_ON_IRQ
Table 5-45. USB Legacy Keyboard State Transitions (Sheet 1 of 2)
Current
State
Data
Value
Next
State
Action
Comment
Standard D1 command. Cycle passed
GateState1 through to 8042. SMI# doesn't go active.
PSTATE (offset C0, bit 6) goes to 1.
64h /
Write
IDLE
IDLE
IDLE
IDLE
IDLE
D1h
Not D1h
N/A
Bit 3 in Config Register determines if cycle
passed through to 8042 and if SMI#
generated.
64h /
Write
IDLE
IDLE
IDLE
IDLE
Bit 2 in Config Register determines if cycle
passed through to 8042 and if SMI#
generated.
64h / Read
Bit 1 in Config Register determines if cycle
passed through to 8042 and if SMI#
generated.
60h /
Write
Don't
Care
Bit 0 in Config Register determines if cycle
passed through to 8042 and if SMI#
generated.
60h / Read
N/A
XXh
Cycle passed through to 8042, even if trap
enabled in Bit 1 in Config Register. No SMI#
GateState2 generated. PSTATE remains 1. If data value
is not DFh or DDh then the 8042 may chose
to ignore it.
60h /
Write
GateState1
198
Datasheet
INTEL [ INTEL ]
