Functional Description
5.19.5
5.19.6
Packet Formats
See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0.
The ICH10 EHCI allows entrance to USB test modes, as defined in the USB 2.0
specification, including Test J, Test Packet, etc. However note that the ICH10 Test
Packet test mode interpacket gap timing may not meet the USB 2.0 specification.
USB 2.0 Interrupts and Error Conditions
Section 4 of the Enhanced Host Controller Interface Specification for Universal Serial
Bus, Revision 1.0 goes into detail on the EHC interrupts and the error conditions that
cause them. All error conditions that the EHC detects can be reported through the EHCI
Interrupt status bits. Only ICH10-specific interrupt and error-reporting behavior is
documented in this section. The EHCI Interrupts Section must be read first, followed by
this section of the datasheet to fully comprehend the EHC interrupt and error-reporting
functionality.
• Based on the EHC’s Buffer sizes and buffer management policies, the Data Buffer
Error can never occur on the ICH10.
• Master Abort and Target Abort responses from hub interface on EHC-initiated read
packets will be treated as Fatal Host Errors. The EHC halts when these conditions
are encountered.
• The ICH10 may assert the interrupts which are based on the interrupt threshold as
soon as the status for the last complete transaction in the interrupt interval has
been posted in the internal write buffers. The requirement in the Enhanced Host
Controller Interface Specification for Universal Serial Bus, Revision 1.0 (that the
status is written to memory) is met internally, even though the write may not be
seen on DMI before the interrupt is asserted.
• Since the ICH10 supports the 1024-element Frame List size, the Frame List
Rollover interrupt occurs every 1024 milliseconds.
• The ICH10 delivers interrupts using PIRQH#.
• The ICH10 does not modify the CERR count on an Interrupt IN when the “Do
Complete-Split” execution criteria are not met.
• For complete-split transactions in the Periodic list, the “Missed Microframe” bit does
not get set on a control-structure-fetch that fails the late-start test. If subsequent
accesses to that control structure do not fail the late-start test, then the “Missed
Microframe” bit will get set and written back.
5.19.6.1
Aborts on USB 2.0-Initiated Memory Reads
If a read initiated by the EHC is aborted, the EHC treats it as a fatal host error. The
following actions are taken when this occurs:
• The Host System Error status bit is set
• The DMA engines are halted after completing up to one more transaction on the
USB interface
• If enabled (by the Host System Error Enable), then an interrupt is generated
• If the status is Master Abort, then the Received Master Abort bit in configuration
space is set
• If the status is Target Abort, then the Received Target Abort bit in configuration
space is set
• If enabled (by the SERR Enable bit in the function’s configuration space), then the
Signaled System Error bit in configuration bit is set.
Datasheet
203
INTEL [ INTEL ]
