Functional Description
5.18.4.7
5.18.5
5.18.6
Cyclic Redundancy Check (CRC)
CRC is used to protect the all non-PID fields in token and data packets. In this context,
these fields are considered to be protected fields. Full details on this are given in the
Universal Serial Bus Specification, Revision 2.0, in Section 8.3.5.
Packet Formats
The USB protocol calls out several packet types: token, data, and handshake packets.
Full details on this are given in the Universal Serial Bus Specification, Revision 2.0, in
Section 8.4.
USB Interrupts
There are two general groups of USB interrupt sources, those resulting from execution
of transactions in the schedule, and those resulting from an ICH10 operation error. All
transaction-based sources can be masked by software through the ICH10’s Interrupt
Enable register. Additionally, individual transfer descriptors can be marked to generate
an interrupt on completion.
When the ICH10 drives an interrupt for USB, it internally drives the PIRQA# pin for USB
function #0 and USB function #3, PIRQD# pin for USB function #1, and the PIRQC#
pin for USB function #2, until all sources of the interrupt are cleared. In order to
accommodate some operating systems, the Interrupt Pin register must contain a
different value for each function of this new multi-function device.
5.18.6.1
Transaction-Based Interrupts
These interrupts are not signaled until after the status for the last complete transaction
in the frame has been written back to host memory. This ensures that software can
safely process through (Frame List Current Index -1) when it is servicing an interrupt.
CRC Error / Time-Out
A CRC/Time-Out error occurs when a packet transmitted from the ICH10 to a USB
device or a packet transmitted from a USB device to the ICH10 generates a CRC error.
The ICH10 is informed of this event by a time-out from the USB device or by the
ICH10’s CRC checker generating an error on reception of the packet. Additionally, a
USB bus time-out occurs when USB devices do not respond to a transaction phase
within 19-bit times of an EOP. Either of these conditions causes the C_ERR field of the
TD to decrement.
When the C_ERR field decrements to 0, the following occurs:
• The Active bit in the TD is cleared
• The Stalled bit in the TD is set
• The CRC/Time-out bit in the TD is set.
• At the end of the frame, the USB Error Interrupt bit is set in the HC status register.
If the CRC/Time out interrupt is enabled in the Interrupt Enable register, a hardware
interrupt will be signaled to the system.
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Datasheet
INTEL [ INTEL ]
