Functional Description
5.6.7
SYNC Field / LDRQ# Rules
Since DMA transfers on LPC are requested through an LDRQ# assertion message, and
are ended through a SYNC field during the DMA transfer, the peripheral must obey the
following rule when initiating back-to-back transfers from a DMA channel.
The peripheral must not assert another message for eight LCLKs after a deassertion is
indicated through the SYNC field. This is needed to allow the 8237, that typically runs
off a much slower internal clock, to see a message deasserted before it is re-asserted
so that it can arbitrate to the next agent.
Under default operation, the host only performs 8-bit transfers on 8-bit channels and
16-bit transfers on 16-bit channels.
The method by which this communication between host and peripheral through system
BIOS is performed is beyond the scope of this specification. Since the LPC host and LPC
peripheral are motherboard devices, no “plug-n-play” registry is required.
The peripheral must not assume that the host is able to perform transfer sizes that are
larger than the size allowed for the DMA channel, and be willing to accept a SIZE field
that is smaller than what it may currently have buffered.
To that end, it is recommended that future devices that may appear on the LPC bus,
that require higher bandwidth than 8-bit or 16-bit DMA allow, do so with a bus
mastering interface and not rely on the 8237.
5.7
8254 Timers (D31:F0)
The ICH10 contains three counters that have fixed uses. All registers and functions
associated with the 8254 timers are in the core well. The 8254 unit is clocked by a
14.31818 MHz clock.
Counter 0, System Timer
This counter functions as the system timer by controlling the state of IRQ0 and is
typically programmed for Mode 3 operation. The counter produces a square wave with
a period equal to the product of the counter period (838 ns) and the initial count value.
The counter loads the initial count value 1 counter period after software writes the
count value to the counter I/O address. The counter initially asserts IRQ0 and
decrements the count value by two each counter period. The counter negates IRQ0
when the count value reaches 0. It then reloads the initial count value and again
decrements the initial count value by two each counter period. The counter then
asserts IRQ0 when the count value reaches 0, reloads the initial count value, and
repeats the cycle, alternately asserting and negating IRQ0.
Counter 1, Refresh Request Signal
This counter provides the refresh request signal and is typically programmed for Mode
2 operation and only impacts the period of the REF_TOGGLE bit in Port 61. The initial
count value is loaded one counter period after being written to the counter I/O address.
The REF_TOGGLE bit will have a square wave behavior (alternate between 0 and 1) and
will toggle at a rate based on the value in the counter. Programming the counter to
anything other than Mode 2 will result in undefined behavior for the REF_TOGGLE bit.
Counter 2, Speaker Tone
This counter provides the speaker tone and is typically programmed for Mode 3
operation. The counter provides a speaker frequency equal to the counter clock
frequency (1.193 MHz) divided by the initial count value. The speaker must be enabled
by a write to port 061h (see NMI Status and Control ports).
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Datasheet
INTEL [ INTEL ]
