Functional Description
5.6.5
5.6.6
Verify Mode
Verify mode is supported on the LPC interface. A verify transfer to the peripheral is
similar to a DMA write, where the peripheral is transferring data to main memory. The
indication from the host is the same as a DMA write, so the peripheral will be driving
data onto the LPC interface. However, the host will not transfer this data into main
memory.
DMA Request Deassertion
An end of transfer is communicated to the ICH10 through a special SYNC field
transmitted by the peripheral. An LPC device must not attempt to signal the end of a
transfer by deasserting LDREQ#. If a DMA transfer is several bytes (e.g., a transfer
from a demand mode device) the ICH10 needs to know when to deassert the DMA
request based on the data currently being transferred.
The DMA agent uses a SYNC encoding on each byte of data being transferred, which
indicates to the ICH10 whether this is the last byte of transfer or if more bytes are
requested. To indicate the last byte of transfer, the peripheral uses a SYNC value of
0000b (ready with no error), or 1010b (ready with error). These encodings tell the
ICH10 that this is the last piece of data transferred on a DMA read (ICH10 to
peripheral), or the byte that follows is the last piece of data transferred on a DMA write
(peripheral to ICH10).
When the ICH10 sees one of these two encodings, it ends the DMA transfer after this
byte and deasserts the DMA request to the 8237. Therefore, if the ICH10 indicated a
16-bit transfer, the peripheral can end the transfer after one byte by indicating a SYNC
value of 0000b or 1010b. The ICH10 does not attempt to transfer the second byte, and
deasserts the DMA request internally.
If the peripheral indicates a 0000b or 1010b SYNC pattern on the last byte of the
indicated size, then the ICH10 only deasserts the DMA request to the 8237 since it does
not need to end the transfer.
If the peripheral wishes to keep the DMA request active, then it uses a SYNC value of
1001b (ready plus more data). This indicates to the 8237 that more data bytes are
requested after the current byte has been transferred, so the ICH10 keeps the DMA
request active to the 8237. Therefore, on an 8-bit transfer size, if the peripheral
indicates a SYNC value of 1001b to the ICH10, the data will be transferred and the DMA
request will remain active to the 8237. At a later time, the ICH10 will then come back
with another START–CYCTYPE–CHANNEL–SIZE etc. combination to initiate another
transfer to the peripheral.
The peripheral must not assume that the next START indication from the ICH10 is
another grant to the peripheral if it had indicated a SYNC value of 1001b. On a single
mode DMA device, the 8237 will re-arbitrate after every transfer. Only demand mode
DMA devices can be assured that they will receive the next START indication from the
ICH10.
Note:
Note:
Indicating a 0000b or 1010b encoding on the SYNC field of an odd byte of a 16-bit
channel (first byte of a 16-bit transfer) is an error condition.
The host stops the transfer on the LPC bus as indicated, fills the upper byte with
random data on DMA writes (peripheral to memory), and indicates to the 8237 that the
DMA transfer occurred, incrementing the 8237’s address and decrementing its byte
count.
Datasheet
117
INTEL [ INTEL ]
