Functional Description
Both count and status of the selected counters may be latched simultaneously. This is
functionally the same as issuing two consecutive, separate Read Back commands. If
multiple count and/or status Read Back commands are issued to the same counters
without any intervening reads, all but the first are ignored.
If both count and status of a counter are latched, the first read operation from that
counter returns the latched status, regardless of which was latched first. The next one
or two reads, depending on whether the counter is programmed for one or two type
counts, returns the latched count. Subsequent reads return unlatched count.
5.8
8259 Interrupt Controllers (PIC) (D31:F0)
The ICH10 incorporates the functionality of two 8259 interrupt controllers that provide
system interrupts for the ISA compatible interrupts. These interrupts are: system
timer, keyboard controller, serial ports, parallel ports, floppy disk, mouse, and DMA
channels. In addition, this interrupt controller can support the PCI based interrupts, by
mapping the PCI interrupt onto the compatible ISA interrupt line. Each 8259 core
supports eight interrupts, numbered 0–7. Table 5-13 shows how the cores are
connected.
.
Table 5-13. Interrupt Controller Core Connections
8259
Input
Typical Interrupt
Source
8259
Connected Pin / Function
0
1
2
3
4
5
6
7
Internal
Internal Timer / Counter 0 output / HPET #0
IRQ1 via SERIRQ
Keyboard
Internal
Slave controller INTR output
IRQ3 via SERIRQ, PIRQ#
Serial Port A
Serial Port B
Master
IRQ4 via SERIRQ, PIRQ#
Parallel Port / Generic IRQ5 via SERIRQ, PIRQ#
Floppy Disk IRQ6 via SERIRQ, PIRQ#
Parallel Port / Generic IRQ7 via SERIRQ, PIRQ#
Internal Real Time
Internal RTC / HPET #1
Clock
0
1
2
Generic
Generic
IRQ9 via SERIRQ, SCI, TCO, or PIRQ#
IRQ10 via SERIRQ, SCI, TCO, or PIRQ#
IRQ11 via SERIRQ, SCI, TCO, or PIRQ#, or HPET
#2
3
4
Generic
IRQ12 via SERIRQ, SCI, TCO, or PIRQ#, or HPET
#3
PS/2 Mouse
Slave
State Machine output based on processor FERR#
assertion. May optionally be used for SCI or TCO
interrupt if FERR# not needed.
5
Internal
SATA Primary (legacy mode), or via SERIRQ or
PIRQ#
6
7
SATA
SATA
SATA Secondary (legacy mode) or via SERIRQ or
PIRQ#
The ICH10 cascades the slave controller onto the master controller through master
controller interrupt input 2. This means there are only 15 possible interrupts for the
ICH10 PIC.
Datasheet
121
INTEL [ INTEL ]
