Functional Description
5.6.2
Abandoning DMA Requests
DMA Requests can be deasserted in two fashions: on error conditions by sending an
LDRQ# message with the ‘ACT’ bit set to 0, or normally through a SYNC field during the
DMA transfer. This section describes boundary conditions where the DMA request needs
to be removed prior to a data transfer.
There may be some special cases where the peripheral desires to abandon a DMA
transfer. The most likely case of this occurring is due to a floppy disk controller which
has overrun or underrun its FIFO, or software stopping a device prematurely.
In these cases, the peripheral wishes to stop further DMA activity. It may do so by
sending an LDRQ# message with the ACT bit as 0. However, since the DMA request was
seen by the ICH10, there is no assurance that the cycle has not been granted and will
shortly run on LPC. Therefore, peripherals must take into account that a DMA cycle may
still occur. The peripheral can choose not to respond to this cycle, in which case the
host will abort it, or it can choose to complete the cycle normally with any random data.
This method of DMA deassertion should be prevented whenever possible, to limit
boundary conditions both on the ICH10 and the peripheral.
5.6.3
General Flow of DMA Transfers
Arbitration for DMA channels is performed through the 8237 within the host. Once the
host has won arbitration on behalf of a DMA channel assigned to LPC, it asserts
LFRAME# on the LPC I/F and begins the DMA transfer. The general flow for a basic DMA
transfer is as follows:
1. ICH10 starts transfer by asserting 0000b on LAD[3:0] with LFRAME# asserted.
2. ICH10 asserts ‘cycle type’ of DMA, direction based on DMA transfer direction.
3. ICH10 asserts channel number and, if applicable, terminal count.
4. ICH10 indicates the size of the transfer: 8 or 16 bits.
5. If a DMA read…
— The ICH10 drives the first 8 bits of data and turns the bus around.
— The peripheral acknowledges the data with a valid SYNC.
— If a 16-bit transfer, the process is repeated for the next 8 bits.
6. If a DMA write…
— The ICH10 turns the bus around and waits for data.
— The peripheral indicates data ready through SYNC and transfers the first byte.
— If a 16-bit transfer, the peripheral indicates data ready and transfers the next
byte.
7. The peripheral turns around the bus.
5.6.4
Terminal Count
Terminal count is communicated through LAD[3] on the same clock that DMA channel is
communicated on LAD[2:0]. This field is the CHANNEL field. Terminal count indicates
the last byte of transfer, based upon the size of the transfer.
For example, on an 8-bit transfer size (SIZE field is 00b), if the TC bit is set, then this is
the last byte. On a 16-bit transfer (SIZE field is 01b), if the TC bit is set, then the
second byte is the last byte. The peripheral, therefore, must internalize the TC bit when
the CHANNEL field is communicated, and only signal TC when the last byte of that
transfer size has been transferred.
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Datasheet
INTEL [ INTEL ]
