Functional Description
The following summarizes the ICH10 integrated Gigabit Ethernet controller features:
• Configurable LED operation for customization of LED display.
• IPv4 and IPv6 Checksum Offload support (receive, transmit, and large send).
• 64-bit address master support for system using more than 4 GB of physical
memory.
• Configurable receive and transmit data FIFO, programmable in 1 KB increments.
• Intelligent interrupt generation to enhance driver performance.
• Compliance with Advanced Configuration and Power Interface and PCI Power
Management standards.
• ACPI register set and power down functionality supporting D0 and D3 states.
• Full wake-up support (APM and ACPI).
• Magic Packet wake-up enable with unique MAC address.
• Fragmented UDP checksum off load for package reassembly.
• Jumbo frames supported.
• LinkSec support (802.3ae compliant)
• TimeSync support (802.1as compliant)
5.3.1
Gigabit Ethernet PCI Bus Interface
The Gigabit Ethernet controller has a PCI interface to the host processor and host
memory. The following sections detail the transaction on the bus.
5.3.1.1
Transaction Layer
The upper layer of the host architecture is the transaction layer. The transaction layer
connects to the device core using an implementation specific protocol. Through this
core-to-transaction-layer protocol, the application-specific parts of the device interact
with the subsystem and transmit and receive requests to or from the remote agent,
respectively.
5.3.1.2
Data Alignment
4 K Boundary
5.3.1.2.1
PCI requests must never specify an Address/Length combination that causes a Memory
Space access to cross a 4 K boundary. It is the HW responsibility to break requests into
4 K-aligned requests (if needed). This does not pose any requirement on SW. However,
if SW allocates a buffer across a 4 K boundary, HW will issue multiple requests for the
buffer. SW should consider aligning buffers to 4 KB boundary in cases where it
improves performance.
The alignment to the 4 K boundaries is done in the core. The Transaction layer will not
do any alignment according to these boundaries.
5.3.1.2.2
5.3.1.3
64 Bytes
PCI requests are multiples of 64 bytes and aligned to make better use of memory
controller resources. Writes, however, can be on any boundary and can cross a 64 byte
alignment boundary
Configuration Request Retry Status
The LAN Controller might have a delay in initialization due to NVM read. If the NVM
configuration read operation is not completed and the device receives a Configuration
Request, the device will respond with a Configuration Request Retry Completion Status
to terminate the Request, and thus effectively stall the Configuration Request until such
time that the subsystem has completed local initialization and is ready to communicate
with the host.
102
Datasheet
INTEL [ INTEL ]
