General Chipset Configuration
6.2.2.7
D02IR—Device 2 Interrupt Route
Offset Address:
Default Value:
314C-314Dh
3210h
Attribute:
Size:
R/W
16 bits
Default
Bits
and
Description
Access
3h
R/W
Interrupt D Pin Route (IDR): Indicates which physical pin INTD# uses
for Device 2.
15:12
11:8
7:4
2h
R/W
Interrupt C Pin Route (ICR): Indicates which physical pin INTC# uses
for Device 2.
1h
R/W
Interrupt B Pin Route (IBR): Indicates which physical pin INTB# uses
for Device 2.
0h
R/W
Interrupt A Pin Route (IAR): Indicates which physical pin INTA# uses
for Device 2.
3:0
6.3
General Configuration Register
6.3.1
RC—RTC Configuration Register
Offset Address:
Default Value:
3400–3403h
00000000h
Attribute:
Size:
RO, R/WLO
32-bit
Default
Bit
and
Description
Access
0000000h
RO
31:3
2
Reserved
Reserved
0b
R/WLO
Upper 128-Byte Lock (UL): When set, bytes 38h–3Fh in the upper
128-byte bank of RTC RAM are locked. Writes will be ignored and reads
will not return any ensured data.
0
1
0
R/WLO
Lower 128-Byte Lock (LL): When set, bytes 38h–3Fh in the lower
128-byte bank of RTC RAM are locked. Writes will be ignored and reads
will not return any ensured data.
0
R/WLO
§ §
80
Datasheet
INTEL [ INTEL ]
