General Chipset Configuration
6.2.1.1
D31IP—Device 31 Interrupt Pin
Offset Address:
Default Value:
3100h–3103h
00000210h
Attribute:
Size:
R/W, RO
32 bits
Bits
Type
Reset
Description
31:4
RO
0
Reserved
LPC Bridge Pin (LIP): The LPC bridge does not generate an
interrupt.
3:0
RO
0h
6.2.1.2
D30IP—Device 30 Interrupt Pin
Offset Address:
Default Value:
3104–3107h
00000321h
Attribute:
Size:
R/W, RO
32 bits
Bits
Type
Reset
Description
31:12
RO
0
Reserved
SDIO Port 2 Interrupt Pin (SD2): Indicates which pin SDIO
Controller 2 uses.
11:8
7:4
R/W
R/W
R/W
3h
SDIO Port 1 Interrupt Pin (SD1: Indicates which pin SDIO
Controller 1 uses.
2h
1h
SDIO Port 0 Interrupt Pin (SD0): Indicates which pin SDIO
Controller 0 uses.
3:0
6.2.1.3
D29IP—Device 29 Interrupt Pin
Offset Address:
Default Value:
3108–310Bh
40000321h
Attribute:
Size:
R/W, RO
32 bits
Bits
Type
Reset
Description
31:28
27:12
11:8
7:4
R/W
RO
4h
0
EHCI Pin (EIP): Indicates which pin the EHCI controller uses.
Reserved
R/W
R/W
R/W
3h
2h
1h
UHCI 2 Pin (U2P): Indicates which pin USB Controller 2 uses.
UHCI 1 Pin (U1P): Indicates which pin USB Controller 1 uses.
UHCI 0 Pin (U0P): Indicates which pin USB Controller 0 uses.
3:0
6.2.1.4
D28IP—Device 28 Interrupt Pin
Offset Address:
Default Value:
310C–310Fh
00000021h
Attribute:
Size:
R/W, RO
32 bits
Bits
Type
Reset
Description
31:8
RO
0
Reserved
PCI Express 2 Pin (P2IP): Indicates which pin PCI Express Port 2
uses.
7:4
3:0
R/W
R/W
2h
PCI Express 1 Pin (P1IP): Indicates which pin PCI Express Port 1
uses.
1h
Datasheet
75
INTEL [ INTEL ]
