Introduction
1.3.2
System Memory Controller
The Intel® SCH integrates a DDR2 memory controller with a single 64-bit wide
interface. Only DDR2 memory is supported. The memory controller interface is fully
configurable through a set of control registers. Features of the Intel® SCH memory
controller include:
• Supports 1.8-V DDR2 SDRAM, up to 2 ranks
• Supports 1.5-V DDR2 SDRAM, 1 rank only
• Supports 400 MT/s and 533 MT/s data rates
• Single 64-bit wide channel
• Single command per clock (1-N) operation
• Support for a maximum of 2GB of DRAM
• Device density support for 512Mb, 1024Mb, and 2048Mb devices
• Device widths of x8 and x16
• Aggressive power management to reduce idle power consumption
• Page closing policies to proactively close pages after idle periods
• No on-die termination (ODT) support
• Supports non-terminated and board-terminated bus topologies
1.3.3
USB Host
The Intel® SCH contains three Universal Host Controller Interface (UHCI) USB 1.1
controllers and an Enhanced Host Controller Interface (EHCI) USB 2.0 controller. Port-
routing logic on the Intel® SCH determines which USB controller is used to operate a
given USB port.
A total of eight USB ports are supported. All eight of these ports are capable of high-
speed data transfers up to 480 MB/s, and six of the ports are also capable of full-speed
and low-speed signaling. The two high-speed-only USB ports may only be used
internally within the system platform.
1.3.4
1.3.5
USB Client
The Intel® SCH supports USB client functionality on Port 2 of the USB interface. This
permits the platform to attach to a separate USB host as a peripheral mass storage
volume or RNDIS device.
PCI Express*
The Intel® SCH has two PCI Express root ports supporting the PCI Express Base
Specification, Revision 1.0a. PCI Express root Ports 1–2 can be statically configured as
two x1 lanes. Each root port supports 2.5 GB/s bandwidth in each direction.
An external graphics device can be used with one of the x1 PCI Express lanes/ports.
1.3.6
LPC Interface
The Intel® SCH implements an LPC interface as described in the LPC 1.1 Specification.
The LPC bridge function of the Intel® SCH resides in PCI Device 31:Function 0.
The LPC interface has three PCI-based clock outputs that may be provided to different
I/O devices, such as Firmware Hub flash memory or a legacy I/O chip. The
LPC_CLKOUT signals run at one-fourth of the H_CLKINP/N frequency and support a
total of six loads (two loads per clock pair) with no external buffering.
24
Datasheet
INTEL [ INTEL ]
