PCI Express* (D28:F0, F1)
11.2.27 LCTL—Link Control Register
Address Offset:
Default Value:
50h-51h
0000h
Attribute:
Size:
R/W, WO, RO
16 bits
Default
Bit
and
Description
Access
00h
RO
15:9
8
Reserved
CLOCKREQ# Enable (CE)
0
R/W
This bit must always be cleared to 0.
Extended Synch (ES)
0
R/W
0 = Extended synch disabled.
1 = Forces extended transmission of FTS ordered sets in FTS and extra
TS2 at exit from L1 prior to entering L0.
7
Common Clock Configuration (CCC)
1 = The Intel® SCH and device are operating with a distributed common
reference clock.
0
R/W
6
5
4
Retrain Link (RL): When set, the root port will train its downstream link.
This bit always returns '0' when read. Software uses LSTS.LT and LSTS.LTE
to check the status of training.
0
R0/WO
Link Disable (LD)
0
R/W
0 = Link enabled.
1 = The root port will disable the link.
0
RO
Read Completion Boundary Control (RCBC): Indicates the read
completion boundary is 64 bytes.
3
2
0
RO
Reserved
Active State Link PM Control (APMC): Indicates whether the root port
should enter L0s or L1 or both.
Bits
Definition
00b
R/W
1:0
00b
01b
10b
11b
Disabled
L0s Entry is Enabled
L1 Entry is Enabled
L0s and L1 Entry Enabled
Datasheet
191
INTEL [ INTEL ]
