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319537-003US 参数 Datasheet PDF下载

319537-003US图片预览
型号: 319537-003US
PDF下载: 下载PDF文件 查看货源
内容描述: 英特尔系统控制器中心 [Intel System Controller Hub]
分类和应用: 控制器
文件页数/大小: 450 页 / 2593 K
品牌: INTEL [ INTEL ]
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Intel® HD Audio (D27:F0)  
10.4  
Vendor Specific Memory Mapped Registers  
10.4.1  
EM1—Extended Mode 1 Register  
Memory Address:  
Default Value:  
1000h  
00000000h  
Attribute:  
Size:  
RO  
32 bits  
Default  
Bit  
and  
Description  
Access  
0
RO  
31:24  
28:28  
Reserved  
00b  
RW  
Loopback Enable (LPBKEN): When set, output data is rerouted to the  
input. Each input has its own loopback enable.  
Free Count Request (FREECNTREQ): This field determines the clock in  
which freecnt will be requested from the XFR layer.  
00  
27:26  
BIOS or software must set FREECNTREQ to “11”  
Any other selection will cause RIRB failures.  
RW  
0b  
Phase Select (PSEL): Sets the input data sample point within phyclk. 1 =  
Phase C, 0 = Phase D  
25  
24  
RW  
Boundary Break (128_4K): Sets the break boundary for reads.  
1b  
0 = 4KB  
RW  
1 = 128B  
CORB Pace (CORBPACE): Determines the rate at which CORB commands  
are issued on the link.  
000b  
RW  
000 = Every Frame  
001 = Every 2 Frames  
......  
23:21  
111 = Every 8 Frames  
FIFO Ready Select (FRS): When cleared, SDS.FRDY is asserted when  
there are 2 or more packets available in the FIFO. When set, SDS.FRDY is  
asserted when there are one or more packets available in the FIFO.  
0b  
20  
19:15  
14  
RW  
00000b  
RO  
Reserved  
48 KHz Enable: When set, Intel® SCH adds one extra bitclk to every  
twelfth frame. When cleared, it will use the normal functionality and send  
500 bitclks per frame.  
0b  
RW  
Dock Enable Signal Transition Select (DETS): When set, DOCK_EN#  
transitions off the falling edge of BCLK (phase C). When cleared,  
DOCK_EN# transitions 1/4 BCLK after the falling edge of BCLK (phase D).  
0b  
13  
RW  
0s  
12:6  
Reserved  
RO  
Input Repeat Count Resets (IRCR): Software writes a 1 to clear the  
respective Repeat Count to 00h. Reads from these bits return 0.  
00b  
WO  
5:4  
3:2  
1:0  
Bit 5 = Input Stream 1 Repeat Count Reset  
Bit 4 = Input Stream 0 Repeat Count Reset  
00b  
RO  
Reserved  
Output Repeat Count Resets (ORCR): Software writes a 1 to clear the  
respective Repeat Count to 00h. Reads from these bits return 0.  
00b  
WO  
Bit 1 = Output Stream 1 Repeat Count Reset  
Bit 0 = Output Stream 0 Repeat Count Reset  
Datasheet  
169