Intel® HD Audio (D27:F0)
10.3.33 SDLPIB—Stream Descriptor Link Position in Buffer
Register
Memory Address:
Input Stream[0]: LBAR + 84h
Input Stream[1]: LBAR + A4h
Output Stream[0]: LBAR + C4h
Output Stream[1]: LBAR + E4h
00000000h
Attribute: RO
Default Value:
Size:
32 bits
Default
Bit
and
Description
Access
Link Position in Buffer: This field indicates the number of bytes that
have been received off the link. This register will count from 0 to the value
in the Cyclic Buffer Length register and then wrap to 0.
0
RO
31:0
10.3.34 SDCBL—Stream Descriptor Cyclic Buffer Length Register
Memory Address:
Input Stream[0]: LBAR + 88h
Input Stream[1]: LBAR + A8h
Output Stream[0]: LBAR + C8h
Output Stream[1]: LBAR + E8h
00000000h
Attribute: R/W
Default Value:
Size:
32 bits
Default
Bit
and
Description
Access
Cyclic Buffer Length: Indicates the number of bytes in the complete
cyclic buffer. This register represents an integer number of samples. Link
Position in Buffer will be reset when it reaches this value.
0
R/W
Software may only write to this register after Global Reset, Controller
Reset, or Stream Reset has occurred. This value should be only modified
when the RUN bit is 0. Once the RUN bit has been set to enable the engine,
software must not write to this register until after the next reset is
asserted, or transfer may be corrupted.
31:0
164
Datasheet
INTEL [ INTEL ]
