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319537-003US 参数 Datasheet PDF下载

319537-003US图片预览
型号: 319537-003US
PDF下载: 下载PDF文件 查看货源
内容描述: 英特尔系统控制器中心 [Intel System Controller Hub]
分类和应用: 控制器
文件页数/大小: 450 页 / 2593 K
品牌: INTEL [ INTEL ]
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Intel® HD Audio (D27:F0)  
10.3.32 SDSTS—Stream Descriptor Status Register  
Memory Address:  
Input Stream[0]: LBAR + 83h  
Input Stream[1]: LBAR + A3h  
Output Stream[0]: LBAR + C3h  
Output Stream[1]: LBAR + E3h  
00h  
Attribute: R/WC, RO  
Default Value:  
Size:  
8 bits  
Default  
Bit  
and  
Description  
Access  
00b  
RO  
7:6  
Reserved  
FIFO Ready (FIFORDY): For output streams, the controller hardware will  
set this bit to 1 while the output DMA FIFO contains enough data to  
maintain the stream on the link. This bit defaults to 0 on reset because the  
FIFO is cleared on a reset.  
0
RO  
5
4
For input streams, the controller hardware will set this bit to 1 when a valid  
descriptor is loaded and the engine is ready for the RUN bit to be set.  
Descriptor Error: When set, this bit indicates that a serious error  
occurred during the fetch of a descriptor. This could be a result of a Master  
Abort, a parity or ECC error on the bus, or any other error which renders  
the current Buffer Descriptor or Buffer Descriptor list useless. This error is  
treated as a fatal stream error, as the stream cannot continue running. The  
RUN bit will be cleared and the stream will stopped.  
0
R/WC  
Software may attempt to restart the stream engine after addressing the  
cause of the error and writing a 1 to this bit to clear it.  
FIFO Error: This bit is set when a FIFO error occurs. This bit is set even if  
an interrupt is not enabled. The bit is cleared by writing a 1 to it.  
For an input stream, this indicates a FIFO overrun occurring while the RUN  
bit is set. When this happens, the FIFO pointers do not increment and the  
incoming data is not written into the FIFO, thereby being lost.  
0
3
R/WC  
For an output stream, this indicates a FIFO underrun when there are still  
buffers to send. The hardware should not transmit anything on the link for  
the associated stream if there is not valid data to send.  
Buffer Completion Interrupt Status: This bit is set to 1 by the hardware  
after the last sample of a buffer has been processed, AND if the Interrupt  
on Completion bit is set in the command byte of the buffer descriptor. It  
remains active until software clears it by writing a 1 to it.  
0
2
R/WC  
00  
RO  
1:0  
Reserved  
Datasheet  
163