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319537-003US 参数 Datasheet PDF下载

319537-003US图片预览
型号: 319537-003US
PDF下载: 下载PDF文件 查看货源
内容描述: 英特尔系统控制器中心 [Intel System Controller Hub]
分类和应用: 控制器
文件页数/大小: 450 页 / 2593 K
品牌: INTEL [ INTEL ]
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Intel® HD Audio (D27:F0)  
(Sheet 2 of 2)  
Default  
and  
Bit  
Description  
Access  
Controller Reset #  
0 = Writing a 0 to this bit causes the Intel HD Audio controller to be  
reset. All state machines, FIFOs and non-resume well memory  
mapped configuration registers (not PCI configuration registers) in  
the controller will be reset. The Intel HD Audio link RESET# signal  
will be asserted, and all other link signals will be driven to their  
default values. After the hardware has completed sequencing into  
the reset state, it will report a 0 in this bit. Software must read a 0  
from this bit to verify the controller is in reset.  
1 = Writing a 1 to this bit causes the controller to exit its reset state and  
deassert the Intel HD Audio link RESET# signal. Software is  
responsible for setting/clearing this bit such that the minimum Intel  
HD Audio link RESET# signal assertion pulse width specification is  
met. When the controller hardware is ready to begin operation, it will  
report a 1 in this bit. Software must read a 1 from this bit before  
accessing any controller registers. This bit defaults to a 0 after  
Hardware reset, therefore, software needs to write a 1 to this bit to  
begin operation.  
0
R/W  
0
NOTES:  
• The CORB/RIRB RUN bits and all stream RUN bits must be verified  
cleared to 0 before writing a 0 to this bit in order to assure a clean  
re-start.  
• When setting or clearing this bit, software must ensure that  
minimum link timing requirements (minimum RESET# assertion  
time, etc.) are met.  
• When this bit is 0 indicating that the controller is in reset, writes to all  
Intel HD Audio memory mapped registers are ignored as if the device  
is not present. The only exception is this register itself. The Global  
Control register is write-able as a DWord, Word, or Byte even when  
CRST# (this bit) is 0 if the byte enable for the byte containing the  
CRST# bit (Byte Enable 0) is active. If Byte Enable 0 is not active,  
writes to the Global Control register will be ignored when CRST# is 0.  
When CRST# is 0, reads to Intel HD Audio memory mapped registers  
will return their default value except for registers that are not reset  
with RESET# or on a D3HOT to D0 transition.  
10.3.7  
STATESTS - State Change Status  
Memory Address:  
Default Value:  
LBAR + 0Eh  
001dh  
Attribute:  
Size:  
RO  
16 bits  
Datasheet  
147