Graphics, Video, and Display (D2:F0)
9.4.4
PCISTS—PCI Status Register
Register Address:
Default Value:
06-07h
00000000h
Attribute:
Size:
RO, R/W
16 bits
Default
Bit
and
Description
Access
0
RO
15:5
4
Reserved
Capability List (CAP): This bit indicates that the register at 34h provides
an offset into PCI Configuration Space containing a pointer to the location
of the first item in the list.
1
RO
0
RO
Interrupt Status (IS): This bit reflects the state of the interrupt in the
device in the graphics device.
3
000b
RO
2:0
Reserved
9.4.5
9.4.6
RID—Revision Identification
Register Address:
Default Value:
08h
Attribute:
Size:
RO
8 bits
See description
Default
Bit
and
Description
Access
00h
RO
Refer to the Intel® System Controller Hub (Intel® SCH) Specification
Update for the value of the Revision ID Register.
7:0
CC—Class Codes Register
Register Address:
Default Value:
09–0Bh
030000h
Attribute:
Size:
RO
24 bits
Default
Bit
and
Description
Access
03h
RO
23:16
15:8
7:0
Base Class Code (BCC): Indicates a display controller.
00h
RO
Sub-Class Code (SCC): When GC.VD is cleared, this value is 00h. When
GC.VD is set, this value is 80h.
00h
RO
Programming Interface (PI): Indicates a display controller.
106
Datasheet
INTEL [ INTEL ]
