Graphics, Video, and Display (D2:F0)
9.3.3.2
SDVO Digital Display Port
Display Pipe A is configured to use the SDVO port. The SDVO port can support a variety
of display types (VGA, LVDS, DVI, TV-Out, etc.) by an external SDVO device. SDVO
devices translate SDVO protocol and timings to the desired display format and timings.
A maximum pixel clock of 160 MHz is supported on the SDVO interface.
9.3.3.2.1
9.3.3.2.2
SDVO DVI/HDMI
DVI (and HDMI), a 3.3-V interface standard supporting the TMDS protocol, is a prime
candidate for SDVO. The Intel® SCH provides an unscaled mode where the display
data is centered within the attached display area. Monitor Hot Plug functionality is
supported.
SDVO LVDS
The Intel® SCH can use the SDVO port to drive an LVDS transmitter. Flat Panel is a
fixed resolution display. The Intel® SCH supports panel fitting in the transmitter,
receiver or an external device, but has no native panel fitting capabilities. The Intel®
SCH provides an unscaled mode where the display data is centered within the attached
display area. Scaling in the LVDS transmitter through the SDVO stall input pair is also
supported.
9.3.3.2.3
SDVO TV-Out
The SDVO port supports both standard and high-definition TV displays in a variety of
formats. The SDVO port generates the proper blank and sync timing, but the external
encoder is responsible for generation of the proper format signal and output timings.
The Intel® SCH will support NTSC/PAL/SECAM standard definition formats. The Intel®
SCH will generate the proper timing for the external encoder. The external encoder is
responsible for generation of the proper format signal.
The TV-out interface on the Intel® SCH is addressable as a master device. This allows
an external TV encoder device to drive a pixel clock signal on
SDVO_TVCLKIN[+/-] that the Intel® SCH uses as a reference frequency. The
frequency of this clock is dependent on the output resolution required.
9.3.3.2.4
9.3.3.2.5
Flicker Filter and Overscan Compensation
The overscan compensation scaling and the flicker filter is done in the external TV
encoder chip. Care must be taken to allow for support of TV sets with high performance
de-interlacers and progressive scan displays connected to by way of a non-interlaced
signal. Timing will be generated with pixel granularity to allow more overscan ratios to
be supported.
Control Bus
The SDVO port defines a two-wire (SDVO_CTRLCLK and SDVO_CTRLDATA)
communication path between the SDVO device and Intel® SCH. Traffic destined for the
PROM or DDC will travel across the Control bus, and will then require the SDVO device
to act as a switch and direct traffic from the Control bus to the appropriate receiver.
The Control bus is able to operate at up to 1 MHz.
Datasheet
103
INTEL [ INTEL ]
