Graphics, Video, and Display (D2:F0)
9.4.10
GMEM_BASE—Graphics Memory Base Address Register
Register Address:
Default Value:
18h–1Bh
00000000h
Attribute:
Size:
RO, R/W
32 bits
This register provides the base address of the graphics aperture within this device.
Accesses to the graphics aperture use the address translation logic of the memory
management unit within the graphics core.
Note:
Accesses to the graphics aperture are only permitted if the internal memory requesters
of the graphics core are not enabled.
Default
Bit
and
Description
Access
000b
R/W
Base Address (BA): Set by the OS, these bits correspond to Address
Signals 31:29.
31:29
28
0b
RO
Reserved
256-MB Address Mask (M256): This bit is either part of the Memory
Base Address (RW) or part of the Address Mask (RO), depending on the
value of MSAC.UAS.
0b
27
R/WLO
0s
RO
26:1
0
Reserved
0
RO
Resource Type (RTE): Indicates a request for memory space.
9.4.11
GTT_BASE—Graphics Translation Table Base Address
Register
Register Address:
Default Value:
1Ch–1Fh
00000000h
Attribute:
Size:
RO, R/W
32 bits
Default
Bit
and
Description
Access
0000h
R/W
Base Address (BA): Set by the OS, these bits correspond to Address
Signals 31:19.
31:19
18
0b
R/WLO
Reserved
256-KB Address Mask (M256): This bit is either part of the GTT Base
Address (RW) or part of the Address Mask (RO), depending on the value
of MSAC.UAS
0b
17
R/WLO
0s
16:1
0
Reserved
RO
0
RO
Resource Type (RTE): Indicates a request for memory space.
108
Datasheet
INTEL [ INTEL ]
