Graphics, Video, and Display (D2:F0)
9.3.2
Display Pipes
The display consists of two pipes:
• Display Pipe A
• Display Pipe B
A pipe consists of a set of combined planes and a timing generator. The timing
generators provide timing information for each of the display pipes. The Intel® SCH
has two independent display pipes, allowing for support of two independent display
streams. A port is the destination for the result of the pipe.
Pipe A can operate in a single-wide mode.
The Clock Generator Units (DPLLA and DPLLB) provide a stable frequency for driving
display devices. It operates by converting an input reference frequency into an output
frequency. The timing generators take their input from internal DPLL devices that are
programmable to generate pixel clocks in the range of 20 MHz–180 MHz.
9.3.3
Display Ports
Display ports are the destination for the display pipe. These are the places where the
display data finally appears to devices outside the graphics device. The Intel® SCH has
one dedicated LVDS port and one SDVO port.
Since the Intel® SCH has two display ports available for its two pipes, it can support up
to two different images on two different display devices. Timings and resolutions for
these two images may be different.
9.3.3.1
LVDS Port
Display Pipe B supports output to the LVDS display port. The LVDS port is programmed
with the panel timing parameters that are determined by installed panel specifications
or read from an onboard EDID ROM. The programmed timing values are then locked
into the registers to prevent unwanted corruption of the values. From that point on, the
display modes are changed by selecting a different source size for that pipe,
programming the VGA registers, or selecting a source size and enabling the VGA. The
timing signals will remain stable and active through mode changes. These mode
changes include VGA to VGA, VGA to HiRes, HiRes to VGA, and HiRes to HiRes.
The transmitter can operate in a variety of modes and supports several data formats.
The serializer supports 6-bit or 8-bit color per lane (for 18-bit and 24-bit color
respectively) and single-channel operating modes. The display stream from the display
pipe is sent to the LVDS transmitter port at the dot clock frequency, which is
determined by the panel timing requirements. The output of LVDS is running at a fixed
multiple of the dot clock frequency.
The single LVDS channel can take 18 or 24 bits of RGB pixel data plus 3 bits of timing
control (HSYNC/VSYNC/DE) and output them on four differential data pair outputs.
This display port is normally used in conjunction with the pipe functions of panel up-
scaling and 6-to 8-bit dither. This display port is also used in conjunction with the panel
power sequencing and additional associated functions.
When enabled, the LVDS constant current drivers consume significant power. Individual
pairs or sets of pairs can be selected to be powered down when not being used. When
disabled, individual or sets of pairs will enter a low power state. When the port is
disabled, all pairs enters a low power mode. The panel power sequencing can be set to
override the selected power state of the drivers during power sequencing.
A maximum pixel clock of 112 MHz is supported for the LVDS interface.
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Datasheet
INTEL [ INTEL ]
