DRAM Controller Registers (D0:F0)
5.1.17
DMIBAR—Root Complex Register Range Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/PCI
68–6Fh
0000000000000000h
RO, RW
Size:
64 bits
This is the base address for the Root Complex configuration space. This window of
addresses contains the Root Complex Register set for the PCI Express Hierarchy
associated with the GMCH. There is no physical memory within this 4 KB window that
can be addressed. The 4 KB reserved by this register does not alias to any PCI 2.3
compliant memory mapped space. On reset, the Root Complex configuration space is
disabled and must be enabled by writing a 1 to DMIBAREN [Dev 0, offset 68h, bit 0].
Bit
Access
Description
63:36
Reserved
RO
0000000h
35:12
RW
000000h
DMI Base Address (DMIBAR): This field corresponds to bits 35:12
of the base address DMI configuration space. BIOS will program this
register resulting in a base address for a 4KB block of contiguous
memory address space. This register ensures that a naturally aligned
4 KB space is allocated within the first 64 GB of addressable memory
space. System Software uses this base address to program the DMI
register set.
11:1
0
Reserved
RO
000h
RW
0b
DMIBAR Enable (DMIBAREN):
0 = DMIBAR is disabled and does not claim any memory
1 = DMIBAR memory mapped accesses are claimed and decoded
appropriately
92
Datasheet
INTEL [ INTEL ]
