Signal Description
2.2
DDR2 DRAM Channel A Interface
Signal Name
Type
Description
SCLK_A[5:0]
O
SDRAM Differential Clock: (3 per DIMM), SCLK_A and its
complement, SCLK_A# make a differential clock pair output.
The crossing of the positive edge of SCLK_A and the
negative edge of its complement SCLK_A# are used to
sample the command and control signals on the SDRAM.
SSTL-1.8
SCLK_A[5:0]#
SCS_A[3:0]#
O
SDRAM Complementary Differential Clock: (3 per
DIMM) These are the complementary differential DDR2
Clock signals.
SSTL-1.8
O
Chip Select: (1 per Rank) These signals select particular
SDRAM components during the active state. There is one
Chip Select for each SDRAM rank.
SSTL-1.8
SMA_A[14:0]
SBS_A[2:0]
O
Memory Address: These signals are used to provide the
multiplexed row and column address to the SDRAM.
SSTL-1.8
O
Bank Select: These signals define which banks are selected
SSTL-1.8
within each SDRAM rank.
DDR2: 1-Gb technology uses 8 banks.
SRAS_A#
SCAS_A#
O
Row Address Strobe: Used with SCAS_A# and SWE_A#
(along with SCS_A#) to define the SDRAM commands.
SSTL-1.8
O
Column Address Strobe: Used with SRAS_A# and
SWE_A# (along with SCS_A#) to define the SDRAM
commands.
SSTL-1.8
SWE_A#
O
Write Enable: Used with SCAS_A# and SRAS_A# (along
SSTL-1.8
with SCS_A#) to define the SDRAM commands.
SDQ_A[63:0]
SDM_A[7:0]
I/O
SSTL-1.8
Data Lines: SDQ_A signals interface to the SDRAM data
bus.
O
Data Mask: When activated during writes, the
corresponding data groups in the SDRAM are masked. There
is one SDM_A bit for every data byte lane.
SSTL-1.8
SDQS_A[7:0]
I/O
SSTL-1.8
Data Strobes: For DDR2, SDQS_A, and its complement
SDQS_A# make up a differential strobe pair. The data is
captured at the crossing point of SDQS_A and its
complement SDQS_A# during read and write transactions.
SDQS_A[7:0]#
SCKE_A[3:0]
I/O
SSTL-1.8
Data Strobe Complements: These are the complementary
DDR2 strobe signals.
O
Clock Enable: (1 per Rank) SCKE_A is used to initialize the
SDRAMs during power-up, to power-down SDRAM ranks,
and to place all SDRAM ranks into and out of self-refresh
during Suspend-to-RAM.
SSTL-1.8
SODT_A[3:0]
O
On Die Termination: Active On-die Termination Control
SSTL-1.8
signals for DDR2 devices.
34
Datasheet
INTEL [ INTEL ]
