Signal Description
Signal Name
Type
Description
HLOCK#
I/O
GTL+
Host Lock: All processor bus cycles sampled with the assertion
of HLOCK# and HADS#, until the negation of HLOCK#, must be
atomic, i.e. no DMI or PCI Express* Graphics accesses to DRAM
are allowed when HLOCK# is asserted by the processor.
HREQ[4:0]#
I/O
GTL+
Host Request Command: Defines the attributes of the
request. HREQ[4:0]# are transferred at 2x rate. Asserted by the
requesting agent during both halves of Request Phase. In the
first half, the signals define the transaction type to a level of
detail that is sufficient to begin a snoop request. In the second
half, the signals carry additional information to define the
complete transaction type.
HTRDY#
O
Host Target Ready: Indicates that the target of the processor
GTL+
transaction is able to enter the data transfer phase.
HRS[2:0]#
O
Response Signals: These signals indicate the type of response
GTL+
according to the following table.
Encoding
000
Response Type
Idle state
001
Retry response
010
Deferred response
011
Reserved(not driven by GMCH)
Hard Failure(not driven by GMCH)
No data response
100
101
110
Implicit Writeback
111
Normal data response
BSEL[2:0]
HRCOMP
I
Bus Speed Select: At the de-assertion of RSTIN#, the value
sampled on these pins determines the expected frequency of the
bus.
CMOS
I/O
Host RCOMP: Used to calibrate the Host GTL+ I/O buffers.
CMOS
This signal is powered by the Host Interface termination rail
(VTT).
HSCOMP
HSCOMP#
HSWING
I/O
CMOS
Slew Rate Compensation: Compensation for the Host
Interface.
I/O
A
Slew Rate Compensation: Compensation for the Host
Interface for falling edges.
I
A
Host Voltage Swing: This signal provides the reference voltage
used by FSB RCOMP circuits. HSWING is used for the signals
handled by HRCOMP.
HDVREF
I
Host Reference Voltage: Voltage input for the Data signals of
A
the Host GTL interface.
HACCVREF
I
Host Reference Voltage: Voltage input for the Address signals
A
of the Host GTL interface.
Datasheet
33
INTEL [ INTEL ]
