Signal Description
Signal Name
Type
Description
RSTIN#
I
Reset In: When asserted, this signal will asynchronously reset
the GMCH logic. This signal is connected to the PCIRST#
output of the Intel® ICH8. All PCI Express Graphics Attach
output signals will also tri-state compliant to PCI Express*
Specification Rev 1.1.
HVIN
This input should have a Schmitt trigger to avoid spurious
resets.
This signal is required to be 3.3V tolerant.
PWROK
EXP_EN
I
Power OK: When asserted, PWROK is an indication to the
GMCH that core power has been stable for at least 10us.
HVIN
I
PCI Express* SDVO Concurrent Select
CMOS
0 = Only SDVO or PCI Express Operational
1 = SDVO and PCI Express operating simultaneously via PCI
Express* Graphics port
EXP_SLR
I
PCI Express* Static Lane Reversal/Form Factor
Selection: GMCH’s PCI Express lane numbers are reversed to
differentiate BTX or ATX form factors.
CMOS
0 = GMCH’s PCI Express lane numbers are reversed (BTX
Platforms)
1 = Normal operation (ATX Platforms)
ICH_SYNC#
TEST[2:0]
O
ICH Sync: See Design Guide for Implementation.
HVCMO
S
I/O
In Circuit Test: These pins should be connected to test points
on the mother board. They are internally shorted to the
package ground and can be used to determine if the corner
balls on the GMCH are correctly soldered down to the
motherboard. These pins should NOT connect to ground on the
motherboard. If TEST[2:0] are not going to be used they
should be left as no connects
2.8
Direct Media Interface (DMI)
Signal Name
Type
Description
DMI_RXP[3:0]
DMI_RXN[3:0]
DMI_TXP[3:0]
DMI_TXN[3:0]
I
Direct Media Interface: Receive differential pair (Rx)
DMI
O
Direct Media Interface: Transmit differential pair (Tx)
DMI
38
Datasheet
INTEL [ INTEL ]
