Signal Description
Signal Name
Type
Description
HDINV[3:0]#
I/O
Dynamic Bus Inversion: Driven along with the HD[63:0]#
signals. Indicates if the associated signals are inverted or not.
HDINV[3:0]# are asserted such that the number of data bits
driven electrically low (low voltage) within the corresponding 16
bit group never exceeds 8.
GTL+
HDINV[x]# Data Bits
HDINV[3]#
HDINV[2]#
HDINV[1]#
HDINV[0]#
HD[63:48]#
HD[47:32]#
HD[31:16]#
HD[15:0]#
HA[35:3]#
I/O
Host Address Bus: HA[35:3]# connect to the processor
address bus. During processor cycles, the HA[35:3]# are inputs.
The GMCH drives HA[35:3]# during snoop cycles on behalf of
DMI and PCI Express* Graphics initiators. HA[35:3]# are
transferred at 2x rate.
GTL+
HADSTB[1:0]#
HD[63:0]#
I/O
GTL+
I/O
Host Address Strobe: The source synchronous strobes used to
transfer HA[35:3]# and HREQ[4:0] at the 2x transfer rate.
Host Data: These signals are connected to the processor data
bus. Data on HD[63:0] is transferred at 4x rate. Note that the
data signals may be inverted on the processor bus, depending
on the HDINV[3:0]# signals.
GTL+
HDSTBP[3:0]#
HDSTBN[3:0]#
I/O
Differential Host Data Strobes: The differential source
synchronous strobes used to transfer HD[63:0]# and
HDINV[3:0]# at 4x transfer rate.
GTL+
Named this way because they are not level sensitive. Data is
captured on the falling edge of both strobes. Hence, they are
pseudo-differential, and not true differential.
Strobes
Bits
Data
HDSTBP3#,
HDSTBN3#
HDINV3#
HD[63:48]#
HDSTBP2#,
HDSTBN2#
HDINV2#
HDINV1#
HDINV0#
HD[47:32]#
HD[31:16]#
HD[15:0]#
HDSTBP1#,
HDSTBN1#
HDSTBP0#,
HDSTBN0#
HHIT#
I/O
Hit: Indicates that a caching agent holds an unmodified version
of the requested line. Also, driven in conjunction with HHITM#
by the target to extend the snoop window.
GTL+
HHITM#
I/O
Hit Modified: Indicates that a caching agent holds a modified
version of the requested line and that this agent assumes
responsibility for providing the line. Also, driven in conjunction
with HHIT# to extend the snoop window.
GTL+
32
Datasheet