Signal Description
Signal Name
Type
Description
GREEN
O
A
GREEN Analog Video Output: This signal is a CRT Analog
video output from the internal color palette DAC. The DAC is
designed for a 37.5 ohm routing impedance, but the terminating
resistor to ground will be 75 ohms (e.g., 75 ohm resistor on the
board, in parallel with a 75 ohm CRT load).
GREEN#
BLUE
O
A
GREEN# Analog Output: This signal is an analog video output
from the internal color palette DAC. It should be shorted to the
ground plane.
O
A
BLUE Analog Video Output: This signal is a CRT Analog video
output from the internal color palette DAC. The DAC is designed
for a 37.5 ohm routing impedance, but the terminating resistor
to ground will be 75 ohms (e.g., 75 ohm resistor on the board,
in parallel with a 75 ohm CRT load).
BLUE#
O
A
BLUE# Analog Output: This signal is an analog video output
from the internal color palette DAC. It should be shorted to the
ground plane.
REFSET
HSYNC
O
A
Resistor Set: Set point resistor for the internal color palette
DAC. A 255 ohm 1% resistor is required between REFSET and
motherboard ground.
O
3.3V
CMOS
CRT Horizontal Synchronization: This signal is used as the
horizontal sync (polarity is programmable) or “sync interval”, 3.3
V output
VSYNC
O
CRT Vertical Synchronization: This signal is used as the
3.3V
CMOS
vertical sync (polarity is programmable) 3.3V output.
DDC_CLK
DDC_DATA
I/O
3.3V
CMOS
Monitor Control Clock
Monitor Control Data
I/O
3.3V
CMOS
2.7
Clocks, Reset, and Miscellaneous
Signal Name
Type
Description
HCLKP
HCLKN
I
Differential Host Clock In: These pins receive a differential
host clock from the external clock synthesizer. This clock is
used by all of the GMCH logic that is in the Host clock domain.
Memory domain clocks are also derived from this source.
HCSL
GCLKP
GCLKN
I
Differential PCI Express* Graphics Clock In: These pins
receive a differential 100 MHz Serial Reference clock from the
external clock synthesizer. This clock is used to generate the
clocks necessary for the support of PCI Express.
HCSL
DREFCLKN
DREFCLKP
I
Display PLL Differential Clock In
HCSL
Datasheet
37
INTEL [ INTEL ]
