Signal Description
2.1
Host Interface Signals
Note: Unless otherwise noted, the voltage level for all signals in this interface is tied to the
termination voltage of the Host Bus (VTT).
Signal Name
Type
Description
HADS#
I/O
Address Strobe: The processor bus owner asserts HADS# to
indicate the first of two cycles of a request phase. The GMCH can
assert this signal for snoop cycles and interrupt messages.
GTL+
HBNR#
HBPRI#
I/O
Block Next Request: Used to block the current request bus
owner from issuing new requests. This signal is used to
dynamically control the processor bus pipeline depth.
GTL+
O
Priority Agent Bus Request: The GMCH is the only Priority
Agent on the processor bus. It asserts this signal to obtain the
ownership of the address bus. This signal has priority over
symmetric bus requests and will cause the current symmetric
owner to stop issuing new transactions unless the HLOCK#
signal was asserted.
GTL+
HBREQ0#
I/O
Bus Request 0: The GMCH pulls the processor’s bus HBREQ0#
signal low during HCPURST#. The processor samples this signal
on the active-to-inactive transition of HCPURST#. The minimum
setup time for this signal is 4 HCLKs. The minimum hold time is
2 clocks and the maximum hold time is 20 HCLKs. HBREQ0#
should be tri-stated after the hold time requirement has been
satisfied.
GTL+
HCPURST#
O
CPU Reset: The HCPURST# pin is an output from the GMCH.
The GMCH asserts HCPURST# while RSTIN# is asserted and for
approximately 1 ms after RSTIN# is de-asserted. The
HCPURST# allows the processors to begin execution in a known
state.
GTL+
Note that the Intel® ICH8 must provide processor frequency
select strap set-up and hold times around HCPURST#. This
requires strict synchronization between GMCH HCPURST# de-
assertion and the Intel® ICH8 driving the straps.
HDBSY#
I/O
GTL+
O
Data Bus Busy: Used by the data bus owner to hold the data
bus for transfers requiring more than one cycle.
HDEFER#
Defer: Signals that the GMCH will terminate the transaction
currently being snooped with either a deferred response or with
a retry response.
GTL+
Datasheet
31
INTEL [ INTEL ]
