Functional Description
10 Functional Description
This chapter provides a functional description of the major interfaces and capabilities
of the GMCH.
10.1
Host Interface
The GMCH supports the Core® 2 Duo processor subset of the Enhanced Mode
Scaleable Bus. The cache line size is 64 bytes. Source synchronous transfer is used for
the address and data signals. The address signals are double pumped, and a new
address can be generated every other bus clock. At 200/266/333MHz bus clock, the
address signals run at 400/533/667 MT/s. The data is quad pumped, and an entire
64B cache line can be transferred in two bus clocks. At 200/266/333 MHz bus clock,
the data signals run at 800/1066/1333 MT/s for a maximum bandwidth of
6.4/8.5/10.7 GB/s.
10.1.1
10.1.2
10.1.3
FSB IOQ Depth
The Scalable Bus supports up to 12 simultaneous outstanding transactions.
FSB OOQ Depth
The GMCH supports only one outstanding deferred transaction on the FSB.
FSB GTL+ Termination
The GMCH integrates GTL+ termination resistors on die. Also, approximately
2.8 pF(fast) – 3.3 pF(slow) per pad of on die capacitance will be implemented to
provide better FSB electrical performance.
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Datasheet
INTEL [ INTEL ]
