Integrated Graphics Device Registers (D2:F0,F1)
8.2.3
PCICMD2—PCI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/1/PCI
04–05h
0000h
RO, RW
16 bits
Size:
This 16-bit register provides basic control over the IGD's ability to respond to PCI
cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master
accesses to main memory.
Bit
Access &
Default
Description
15:10
Reserved
RO
0s
9
8
7
6
Fast Back-to-Back (FB2B): Not Implemented. Hardwired to 0.
SERR Enable (SERRE): Not Implemented. Hardwired to 0.
RO
0b
RO
0b
Address/Data Stepping Enable (ADSTEP): Not Implemented.
Hardwired to 0.
RO
0b
Parity Error Enable (PERRE): Not Implemented. Hardwired to 0.
Since the IGD belongs to the category of devices that does not corrupt
programs or data in system memory or hard drives, the IGD ignores
any parity error that it detects and continues with normal operation.
RO
0b
5
4
3
2
RO
0b
VGA Palette Snoop Enable (VGASNOOP): This bit is hardwired to 0
to disable snooping.
RO
0b
Memory Write and Invalidate Enable (MWIE): Hardwired to 0.
The IGD does not support memory write and invalidate commands.
RO
0b
Special Cycle Enable (SCE): This bit is hardwired to 0. The IGD
ignores Special cycles.
RW
0b
Bus Master Enable (BME):
0 = Disable IGD bus mastering.
1 = Enable the IGD to function as a PCI compliant master.
1
0
RW
0b
Memory Access Enable (MAE): This bit controls the IGD's response
to memory space accesses.
0 = Disable.
1 = Enable.
RW
0b
I/O Access Enable (IOAE): This bit controls the IGD's response to
I/O space accesses.
0 = Disable.
1 = Enable.
250
Datasheet
INTEL [ INTEL ]
