Integrated Graphics Device Registers (D2:F0,F1)
8.2.4
PCISTS2—PCI Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/1/PCI
06–07h
0090h
RO
Size:
16 bits
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant
master abort and PCI compliant target abort. PCISTS also indicates the DEVSEL#
timing that has been set by the IGD.
Bit
15
Access &
Default
Description
RO
0b
Detected Parity Error (DPE): Since the IGD does not detect parity,
this bit is always hardwired to 0.
14
RO
0b
Signaled System Error (SSE): The IGD never asserts SERR#,
therefore this bit is hardwired to 0.
13
RO
0b
Received Master Abort Status (RMAS): The IGD never gets a
Master Abort, therefore this bit is hardwired to 0.
12
RO
0b
Received Target Abort Status (RTAS): The IGD never gets a
Target Abort, therefore this bit is hardwired to 0.
11
RO
0b
Signaled Target Abort Status (STAS): Hardwired to 0. The IGD
does not use target abort semantics.
10:9
8
RO
00b
DEVSEL Timing (DEVT): N/A. These bits are hardwired to 00.
RO
0b
Master Data Parity Error Detected (DPD): Since Parity Error
Response is hardwired to disabled (and the IGD does not do any
parity detection), this bit is hardwired to 0.
7
6
5
4
RO
1b
Fast Back-to-Back (FB2B): Hardwired to 1. The IGD accepts fast
back-to-back when the transactions are not to the same agent.
RO
0b
User Defined Format (UDF): Hardwired to 0.
RO
0b
66 MHz PCI Capable (66C): N/A - Hardwired to 0.
RO
1b
Capability List (CLIST): This bit is set to 1 to indicate that the
register at 34h provides an offset into the function's PCI Configuration
Space containing a pointer to the location of the first item in the list.
3
RO
0b
Interrupt Status (INTSTS): Hardwired to 0.
2:0
RO
Reserved
000b
Datasheet
251
INTEL [ INTEL ]
