PCI Express* Registers (D1:F0)
Bit
Access &
Default
Description
Hot-plug Interrupt Enable (HPIE):
5
RO
0b
0 = Disable
1 = Enables generation of an interrupt on enabled hot-plug events
Default value of this field is 0b. If the Hot Plug Capable field in
the Slot Capabilities register is set to 0b, this bit is permitted to
be read-only with a value of 0b.
4
RO
0b
Command Completed Interrupt Enable (CCI): If Command
Completed notification is supported (as indicated by No Command
Completed Support field of Slot Capabilities Register), when set to 1b,
this bit enables software notification when a hot-plug command is
completed by the Hot-Plug Controller.
If Command Completed notification is not supported, this bit must be
hardwired to 0b.
3
2
RW
0b
Presence Detect Changed Enable (PDCE):
0 = Disable
1 = Enables software notification on a presence detect changed
event.
RO
0b
MRL Sensor Changed Enable (MSCE): If the MRL Sensor Present
field in the Slot Capabilities register is set to 0b, this bit is permitted
to be read-only with a value of 0b.
0 = Disable (default)
1 = Enables software notification on a MRL sensor changed event.
1
0
RO
0b
Power Fault Detected Enable (PFDE): If Power Fault detection is
not supported, this bit is permitted to be read-only with a value of 0b.
0 = Disable (default)
1 = Enables software notification on a power fault event.
Attention Button Pressed Enable (ABPE):
0 = Disable (default)
RO
0b
1 = Enables software notification on an attention button pressed
event.
200
Datasheet
INTEL [ INTEL ]
