PCI Express* Registers (D1:F0)
Bit
Access &
Default
Description
4
RO
0b
Power Indicator Present (PIP):
0 = No power indicator
1 = A Power Indicator is electrically controlled by the chassis for this
slot.
3
2
1
RO
0b
Attention Indicator Present (AIP):
0 = No Attention indicator
1 = An Attention Indicator is electrically controlled by the chassis.
MRL Sensor Present (MSP):
RO
0b
0 = No MRL sensor
1 = MRL Sensor is implemented on the chassis for this slot.
Power Controller Present (PCP):
0 = No power controller
RO
0b
1 = A software programmable Power Controller is implemented for
this slot/adapter (depending on form factor).
0
RO
0b
Attention Button Present (ABP):
0 = No attention button
1 = An Attention Button for this slot is electrically controlled by the
chassis.
6.1.42
SLOTCTL—Slot Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/PCI
B8–B9h
01C0h
RO, RW
16 bits
Size:
PCI Express Slot related registers allow for the support of Hot Plug.
Bit
15:13
12
Access &
Default
Description
RO
000b
Reserved
RO
0b
Data Link Layer State Changed Enable (DLLSCE): If the Data
Link Layer Link Active capability is implemented, when set to 1b, this
field enables software notification when Data Link Layer Link Active
field is changed.
11
RO
0b
Electromechanical Interlock Control (EIC): If an
Electromechanical Interlock is implemented, a write of 1b to this field
causes the state of the interlock to toggle. A write of 0b to this field
has no effect. A read to this register always returns a 0.
198
Datasheet
INTEL [ INTEL ]
