DRAM Controller Registers (D0:F0)
5.3.4
EPLE2D— Controller Link Entry 2 Description
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/PXPEPBAR
60–63h
02000002h
RO, RWO
Size:
32 bits
This register provides the first part of a Link Entry which declares an internal link to
another Root Complex Element.
Bit
Access &
Default
Description
31:24
RO
02h
Target Port Number (TPN): This field specifies the port number
associated with the element targeted by this link entry (PEG). The
target port number is with respect to the component that contains
this element as specified by the target component ID.
23:16
RWO
00h
Target Component ID (TCID): This field indicates the physical or
logical component that is targeted by this link entry. A value of 0 is
reserved. Component IDs start at 1. This value is a mirror of the
value in the Component ID field of all elements in this component.
15:2
1
RO
0s
Reserved
RO
1b
Link Type (LTYP): This field indicates that the link points to
configuration space of the integrated device which controls the x16
root port.
The link address specifies the configuration address (segment, bus,
device, function) of the target root port.
0
RWO
0b
Link Valid (LV):
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
160
Datasheet
INTEL [ INTEL ]
